{"id":"https://openalex.org/W2033287736","doi":"https://doi.org/10.1145/2483028.2483094","title":"Multi-corner multi-voltage domain clock mesh design","display_name":"Multi-corner multi-voltage domain clock mesh design","publication_year":2013,"publication_date":"2013-05-02","ids":{"openalex":"https://openalex.org/W2033287736","doi":"https://doi.org/10.1145/2483028.2483094","mag":"2033287736"},"language":"en","primary_location":{"id":"doi:10.1145/2483028.2483094","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2483028.2483094","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033656893","display_name":"Can Sitik","orcid":"https://orcid.org/0000-0003-0056-2137"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Can Sitik","raw_affiliation_strings":["Drexel University, Philadelphia, PA, USA","Drexel University, Philadelphia, PA, USA;"],"affiliations":[{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]},{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA;","institution_ids":["https://openalex.org/I72816309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081080799","display_name":"Bar\u0131\u015f Ta\u015fk\u0131n","orcid":"https://orcid.org/0000-0002-7631-5696"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Baris Taskin","raw_affiliation_strings":["Drexel University, Philadelphia, PA, USA","Drexel University, Philadelphia, PA, USA;"],"affiliations":[{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]},{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA;","institution_ids":["https://openalex.org/I72816309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5033656893"],"corresponding_institution_ids":["https://openalex.org/I72816309"],"apc_list":null,"apc_paid":null,"fwci":0.6196907,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.74647173,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"209","last_page":"214"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.6947588920593262},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.5675069093704224},{"id":"https://openalex.org/keywords/cpu-core-voltage","display_name":"CPU core voltage","score":0.5528004765510559},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5415135025978088},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44547489285469055},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.41671550273895264},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.4133490324020386},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3458384871482849},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2556620240211487},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24447783827781677},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.23187163472175598},{"id":"https://openalex.org/keywords/voltage-divider","display_name":"Voltage divider","score":0.18078643083572388},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09039449691772461},{"id":"https://openalex.org/keywords/voltage-droop","display_name":"Voltage droop","score":0.08430960774421692},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.05050152540206909}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.6947588920593262},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.5675069093704224},{"id":"https://openalex.org/C55038917","wikidata":"https://www.wikidata.org/wiki/Q453979","display_name":"CPU core voltage","level":5,"score":0.5528004765510559},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5415135025978088},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44547489285469055},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.41671550273895264},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.4133490324020386},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3458384871482849},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2556620240211487},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24447783827781677},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.23187163472175598},{"id":"https://openalex.org/C49324399","wikidata":"https://www.wikidata.org/wiki/Q466758","display_name":"Voltage divider","level":3,"score":0.18078643083572388},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09039449691772461},{"id":"https://openalex.org/C40760162","wikidata":"https://www.wikidata.org/wiki/Q10920295","display_name":"Voltage droop","level":4,"score":0.08430960774421692},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.05050152540206909}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2483028.2483094","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2483028.2483094","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8299999833106995}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1985843314","https://openalex.org/W2011647964","https://openalex.org/W2032024709","https://openalex.org/W2040589244","https://openalex.org/W2052797491","https://openalex.org/W2076139224","https://openalex.org/W2099984646","https://openalex.org/W2121252299","https://openalex.org/W2121711235","https://openalex.org/W2127588614","https://openalex.org/W2133916137"],"related_works":["https://openalex.org/W2164834710","https://openalex.org/W4232019485","https://openalex.org/W2199871724","https://openalex.org/W4327499872","https://openalex.org/W2123512677","https://openalex.org/W2000684372","https://openalex.org/W2163318442","https://openalex.org/W2028052815","https://openalex.org/W2066822161","https://openalex.org/W2954620240"],"abstract_inverted_index":{"This":[0],"paper":[1],"introduces":[2],"a":[3,21,50,64,143,172,179,183],"novel":[4,65],"multi-voltage":[5,19,115,154,173],"domain":[6,48,116,147,155,174],"clock":[7,23,41,84,117,138,148,156,175],"mesh":[8,24,118,157,176],"design":[9],"methodology":[10],"that":[11,25],"is":[12,30,69],"effective":[13],"under":[14],"multiple":[15,27,87],"process":[16,109],"corners.":[17],"In":[18],"designs,":[20],"single":[22,145,180],"spans":[26],"voltage":[28,37,47,88,146],"domains":[29],"infeasible":[31],"due":[32,79],"to":[33,60,71,80,122],"the":[34,40,44,73,81,94,137,160],"incompatibility":[35],"of":[36,39,75,83,136,163],"levels":[38],"drivers":[42],"on":[43,126,140,169],"electrically-shorted":[45],"mesh-each":[46],"requires":[49],"separate":[51],"mesh.":[52],"The":[53,90,114],"skew":[54,162],"among":[55],"these":[56],"isolated":[57],"meshes":[58,85],"need":[59],"be":[61],"matched":[62],"and":[63,107,150],"premesh":[66],"tree":[67],"synthesis":[68],"required":[70],"tolerate":[72],"impact":[74],"PVT":[76],"variations":[77],"exacerbated":[78],"separation":[82],"for":[86,178,190],"levels.":[89],"experiments":[91],"performed":[92],"with":[93,128,182],"largest":[95],"three":[96],"ISCAS'89":[97],"benchmark":[98],"circuits":[99],"operating":[100],"at":[101],"500":[102],"MHz,":[103],"90":[104],"nm":[105],"technology":[106],"3":[108],"corners":[110,165],"show":[111],"that:":[112],"1)":[113],"can":[119,158],"achieve":[120],"up":[121],"42%":[123],"lower":[124],"power":[125,187],"average":[127,141,170],"39.04":[129],"ps":[130,168],"skew,":[131],"as":[132,134],"low":[133],"\u22481.95%":[135],"period,":[139],"over":[142,171],"typical":[144],"mesh,":[149],"2)":[151],"multi-corner":[152],"optimized":[153,177],"decrease":[159],"global":[161],"all":[164],"by":[166],"190.42":[167],"corner":[181],"15%":[184],"degradation":[185],"in":[186],"consumption":[188],"necessary":[189],"variation-tolerance.":[191]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}