{"id":"https://openalex.org/W1993679085","doi":"https://doi.org/10.1145/2483028.2483089","title":"Efficient transistor-level design of CMOS gates","display_name":"Efficient transistor-level design of CMOS gates","publication_year":2013,"publication_date":"2013-05-02","ids":{"openalex":"https://openalex.org/W1993679085","doi":"https://doi.org/10.1145/2483028.2483089","mag":"1993679085"},"language":"en","primary_location":{"id":"doi:10.1145/2483028.2483089","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2483028.2483089","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031641596","display_name":"Vinicius N. Possani","orcid":"https://orcid.org/0000-0003-4334-1174"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Vinicius Neves Possani","raw_affiliation_strings":["Federal University of Pelotas, Pelotas, Brazil","Federal University of Pelotas, Pelotas, Brazil,"],"affiliations":[{"raw_affiliation_string":"Federal University of Pelotas, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Federal University of Pelotas, Pelotas, Brazil,","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5105354099","display_name":"Vinicius Callegaro","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Vinicius Callegaro","raw_affiliation_strings":["Federal University of Rio Grande do Sul, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065397615","display_name":"Andr\u00e9 I. Reis","orcid":"https://orcid.org/0000-0002-3118-8160"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Andr\u00e9 In\u00e1cio Reis","raw_affiliation_strings":["Federal University of Rio Grande do Sul, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090563366","display_name":"Renato P. Ribas","orcid":"https://orcid.org/0000-0002-9895-7489"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Renato Perez Ribas","raw_affiliation_strings":["Federal University of Rio Grande do Sul, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068796829","display_name":"Felipe Marques","orcid":"https://orcid.org/0000-0003-1318-9992"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Felipe de Souza Marques","raw_affiliation_strings":["Federal University of Pelotas, Pelotas, Brazil","Federal University of Pelotas, Pelotas, Brazil,"],"affiliations":[{"raw_affiliation_string":"Federal University of Pelotas, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Federal University of Pelotas, Pelotas, Brazil,","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014303947","display_name":"Leomar S. da Rosa","orcid":"https://orcid.org/0000-0002-7150-5685"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Leomar Soares da Rosa Junior","raw_affiliation_strings":["Federal University of Pelotas, Pelotas, Brazil","Federal University of Pelotas, Pelotas, Brazil,"],"affiliations":[{"raw_affiliation_string":"Federal University of Pelotas, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Federal University of Pelotas, Pelotas, Brazil,","institution_ids":["https://openalex.org/I169248161"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5031641596"],"corresponding_institution_ids":["https://openalex.org/I169248161"],"apc_list":null,"apc_paid":null,"fwci":0.2364,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.58436811,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"191","last_page":"196"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.7327950596809387},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6872012615203857},{"id":"https://openalex.org/keywords/transistor-count","display_name":"Transistor count","score":0.6418488621711731},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6335344910621643},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6235513091087341},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5118595957756042},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.49419358372688293},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.48704126477241516},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4765630066394806},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.47142642736434937},{"id":"https://openalex.org/keywords/series","display_name":"Series (stratigraphy)","score":0.4145088195800781},{"id":"https://openalex.org/keywords/transistor-model","display_name":"Transistor model","score":0.4132387340068817},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2710491120815277},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2471892237663269},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22354039549827576},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.15565329790115356},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11591488122940063},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09902045130729675}],"concepts":[{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.7327950596809387},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6872012615203857},{"id":"https://openalex.org/C196320899","wikidata":"https://www.wikidata.org/wiki/Q2623746","display_name":"Transistor count","level":4,"score":0.6418488621711731},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6335344910621643},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6235513091087341},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5118595957756042},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.49419358372688293},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.48704126477241516},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4765630066394806},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.47142642736434937},{"id":"https://openalex.org/C143724316","wikidata":"https://www.wikidata.org/wiki/Q312468","display_name":"Series (stratigraphy)","level":2,"score":0.4145088195800781},{"id":"https://openalex.org/C150169584","wikidata":"https://www.wikidata.org/wiki/Q7834319","display_name":"Transistor model","level":4,"score":0.4132387340068817},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2710491120815277},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2471892237663269},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22354039549827576},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.15565329790115356},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11591488122940063},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09902045130729675},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2483028.2483089","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2483028.2483089","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.75,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1511688816","https://openalex.org/W1994996301","https://openalex.org/W2015987974","https://openalex.org/W2031298013","https://openalex.org/W2033704098","https://openalex.org/W2040537281","https://openalex.org/W2055005167","https://openalex.org/W2078179095","https://openalex.org/W2087907893","https://openalex.org/W2105789204","https://openalex.org/W2141516637","https://openalex.org/W2144613608","https://openalex.org/W2151525909","https://openalex.org/W2159683499","https://openalex.org/W2170230760"],"related_works":["https://openalex.org/W2072989701","https://openalex.org/W1738647919","https://openalex.org/W3000179092","https://openalex.org/W1986774039","https://openalex.org/W2050511294","https://openalex.org/W2118321428","https://openalex.org/W2137494283","https://openalex.org/W2329434788","https://openalex.org/W2895902477","https://openalex.org/W1583771840"],"abstract_inverted_index":{"The":[0,84],"transistor":[1,38,58,71],"arrangement":[2],"optimization":[3],"is":[4,48,66],"an":[5,42],"effective":[6],"possibility":[7],"to":[8,18,35,50,68,96],"improve":[9],"VLSI":[10],"design,":[11],"especially":[12],"when":[13,94],"generating":[14],"CMOS":[15],"logic":[16],"gates":[17],"be":[19],"inserted":[20],"in":[21],"standard":[22],"cell":[23],"libraries.":[24],"This":[25],"paper":[26],"addresses":[27],"this":[28,92],"issue":[29],"and":[30,53],"presents":[31],"a":[32],"new":[33],"methodology":[34,93],"generate":[36],"efficient":[37],"networks.":[39],"Starting":[40],"from":[41],"input":[43],"ISOP,":[44],"the":[45,62,81,89],"proposed":[46,63],"method":[47],"capable":[49],"deliver":[51],"series-parallel":[52],"non-series-parallel":[54],"arrangements":[55,72],"with":[56],"reduced":[57],"count.":[59],"By":[60],"applying":[61],"approach,":[64],"it":[65],"possible":[67],"achieve":[69],"optimized":[70],"since":[73],"greedy":[74],"choices":[75],"are":[76],"avoided":[77],"during":[78],"part":[79],"of":[80,91],"generation":[82],"process.":[83],"performed":[85],"experiments":[86],"have":[87],"demonstrated":[88],"efficiency":[90],"comparing":[95],"other":[97],"available":[98],"techniques.":[99]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}