{"id":"https://openalex.org/W2019690221","doi":"https://doi.org/10.1145/2483028.2483083","title":"A source-synchronous Htree-based network-on-chip","display_name":"A source-synchronous Htree-based network-on-chip","publication_year":2013,"publication_date":"2013-05-02","ids":{"openalex":"https://openalex.org/W2019690221","doi":"https://doi.org/10.1145/2483028.2483083","mag":"2019690221"},"language":"en","primary_location":{"id":"doi:10.1145/2483028.2483083","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2483028.2483083","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109806634","display_name":"Ayan Mandal","orcid":null},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ayan Mandal","raw_affiliation_strings":["Texas A&amp;M University, College Station, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&amp;M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021685706","display_name":"Sunil P. Khatri","orcid":"https://orcid.org/0000-0001-7134-9929"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sunil P. Khatri","raw_affiliation_strings":["Texas A&amp;M University, College Station, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&amp;M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103702897","display_name":"Rabi Mahapatra","orcid":"https://orcid.org/0000-0003-1702-8045"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rabi N. Mahapatra","raw_affiliation_strings":["Texas A&amp;M University, College Station, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&amp;M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.12022496,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"161","last_page":"166"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10179","display_name":"Supercapacitor Materials and Fabrication","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2504","display_name":"Electronic, Optical and Magnetic Materials"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.730911374092102},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6482089161872864},{"id":"https://openalex.org/keywords/ring-network","display_name":"Ring network","score":0.6243682503700256},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.5791438221931458},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.5605798959732056},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5391616225242615},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5262907147407532},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4432377219200134},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.42652779817581177},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.41914474964141846},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.4140760600566864},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3474119305610657},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32969704270362854},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2942242920398712},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.1742766797542572},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1275075078010559}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.730911374092102},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6482089161872864},{"id":"https://openalex.org/C122306262","wikidata":"https://www.wikidata.org/wiki/Q719775","display_name":"Ring network","level":3,"score":0.6243682503700256},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.5791438221931458},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.5605798959732056},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5391616225242615},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5262907147407532},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4432377219200134},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.42652779817581177},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.41914474964141846},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.4140760600566864},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3474119305610657},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32969704270362854},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2942242920398712},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.1742766797542572},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1275075078010559},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2483028.2483083","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2483028.2483083","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1571966117","https://openalex.org/W2018562346","https://openalex.org/W2042876290","https://openalex.org/W2048789167","https://openalex.org/W2066162922","https://openalex.org/W2121416636","https://openalex.org/W2123184444","https://openalex.org/W2141184219","https://openalex.org/W2147657366","https://openalex.org/W2148371977","https://openalex.org/W2150585795","https://openalex.org/W2154323564","https://openalex.org/W2157488385","https://openalex.org/W2170639273","https://openalex.org/W3169463464","https://openalex.org/W6634113760"],"related_works":["https://openalex.org/W2052455055","https://openalex.org/W4386968318","https://openalex.org/W2133326759","https://openalex.org/W2169622190","https://openalex.org/W3006003651","https://openalex.org/W2294981364","https://openalex.org/W2174922170","https://openalex.org/W2286776167","https://openalex.org/W2377749234","https://openalex.org/W2474747038"],"abstract_inverted_index":{"Most":[0],"existing":[1],"Network-on-Chip":[2],"(NoC)":[3],"designs":[4,248,281],"operate":[5],"at":[6],"the":[7,14,33,46,56,59,68,122,132,142,147,158,169,184,190,197,227,230,239,245,274,301,304,317],"same":[8],"or":[9],"lower":[10,42,252,289],"clock":[11,52,95,98,129,137],"speed":[12,134],"as":[13],"processing":[15],"elements":[16],"(PEs).":[17],"Recently,":[18],"a":[19,37,50,63,75,94,126,262,271,297],"new":[20,179],"source-synchronous":[21],"ring-based":[22,47,78,135],"NoC":[23,57,174,181,193,201,210,247,280,308,314],"architecture":[24],"has":[25],"been":[26],"proposed,":[27],"which":[28,110],"runs":[29],"significantly":[30,38,251],"faster":[31],"than":[32],"PEs":[34,123,143],"and":[35,41,58,61,101,220,237,257,288,303],"offers":[36],"higher":[39,263],"bandwidth":[40],"communication":[43],"latency.":[44,223],"However,":[45],"design":[48,120],"assumes":[49],"separate":[51],"distribution":[53],"scheme":[54],"for":[55,67],"PEs,":[60],"uses":[62],"standard":[64],"mesh":[65],"topology":[66],"NoC.":[69,159],"In":[70,183],"this":[71,186],"work,":[72],"we":[73,176],"present":[74],"source":[76,172,199],"synchronous":[77,145,173,200],"NoC,":[79],"laid":[80,113],"out":[81,114],"in":[82,115,168,214],"an":[83,116,307],"H-tree":[84,117,170,191],"topology,":[85],"with":[86,146,157],"each":[87,206],"data":[88],"link":[89,218],"being":[90],"routed":[91],"parallel":[92],"to":[93,124,194,260,270,296],"ring.":[96],"The":[97,203],"is":[99,212],"generated":[100],"distributed":[102],"by":[103,138,164,233],"multiple":[104],"standing":[105],"wave":[106],"oscillator":[107],"(SWO)":[108],"rings,":[109],"are":[111,144,258],"also":[112,161,225],"topology.":[118],"Our":[119],"allows":[121],"extract":[125],"low":[127],"jitter":[128],"directly":[130],"from":[131],"high":[133],"SWO":[136],"division.":[139],"Moreover,":[140,277],"since":[141],"ring":[148],"clock,":[149],"they":[150],"do":[151],"not":[152],"need":[153],"synchronizers":[154],"while":[155],"communicating":[156],"We":[160,224],"show":[162,243],"that":[163,244],"recursively":[165],"duplicating":[166],"links":[167],"based":[171,192],"(Hnoc),":[175],"can":[177,249,310],"obtain":[178],"hybrid":[180,209,231,246,279,313],"structures.":[182],"limit,":[185],"recursive":[187],"duplication":[188],"causes":[189],"morph":[195],"into":[196],"meshbased":[198],"(Mnoc).":[202],"performance":[204,228,302],"of":[205,216,229,273],"such":[207],"intermediate":[208],"structure":[211,315],"quantified":[213],"terms":[215],"area,":[217],"utilization":[219],"contention":[221],"free":[222],"enhance":[226],"NoCs":[232],"widening":[234],"congested":[235],"links,":[236],"quantify":[238],"tradeoffs.":[240],"Experimental":[241],"results":[242],"provide":[250],"latency":[253],"(upto":[254,266,285,292],"5\u00d7":[255],"lower)":[256,294],"able":[259],"sustain":[261],"injection":[264],"rate":[265],"6.8\u00d7":[267],"higher)":[268],"compared":[269,295],"state":[272],"art":[275],"mesh.":[276,298],"these":[278],"use":[282],"fewer":[283],"buffers":[284],"19.4%":[286],"less)":[287],"wire":[290],"length":[291],"19.7%":[293],"Based":[299],"on":[300],"area":[305],"tradeoffs,":[306],"designer":[309],"select":[311],"any":[312],"among":[316],"presented.":[318]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
