{"id":"https://openalex.org/W2142927744","doi":"https://doi.org/10.1145/2483028.2483059","title":"Skew-bounded low swing clock tree optimization","display_name":"Skew-bounded low swing clock tree optimization","publication_year":2013,"publication_date":"2013-05-02","ids":{"openalex":"https://openalex.org/W2142927744","doi":"https://doi.org/10.1145/2483028.2483059","mag":"2142927744"},"language":"en","primary_location":{"id":"doi:10.1145/2483028.2483059","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2483028.2483059","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033656893","display_name":"Can Sitik","orcid":"https://orcid.org/0000-0003-0056-2137"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Can Sitik","raw_affiliation_strings":["Drexel University, Philadelphia, PA, USA","Drexel University, Philadelphia, PA, USA;"],"affiliations":[{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]},{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA;","institution_ids":["https://openalex.org/I72816309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081080799","display_name":"Bar\u0131\u015f Ta\u015fk\u0131n","orcid":"https://orcid.org/0000-0002-7631-5696"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Baris Taskin","raw_affiliation_strings":["Drexel University, Philadelphia, PA, USA","Drexel University, Philadelphia, PA, USA;"],"affiliations":[{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]},{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA;","institution_ids":["https://openalex.org/I72816309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5033656893"],"corresponding_institution_ids":["https://openalex.org/I72816309"],"apc_list":null,"apc_paid":null,"fwci":1.1822,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.82212917,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"49","last_page":"54"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.8953518867492676},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.857530951499939},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7812792658805847},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.7184315919876099},{"id":"https://openalex.org/keywords/swing","display_name":"Swing","score":0.7084549069404602},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6584288477897644},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.6498529314994812},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.5692882537841797},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.537514865398407},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4877987205982208},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47975456714630127},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.3945307731628418},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.21829989552497864},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2109794318675995},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.20576274394989014},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.17779231071472168},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08991318941116333}],"concepts":[{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.8953518867492676},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.857530951499939},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7812792658805847},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.7184315919876099},{"id":"https://openalex.org/C65655974","wikidata":"https://www.wikidata.org/wiki/Q14867674","display_name":"Swing","level":2,"score":0.7084549069404602},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6584288477897644},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6498529314994812},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.5692882537841797},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.537514865398407},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4877987205982208},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47975456714630127},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.3945307731628418},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.21829989552497864},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2109794318675995},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.20576274394989014},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.17779231071472168},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08991318941116333},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2483028.2483059","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2483028.2483059","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8700000047683716}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1588355149","https://openalex.org/W2011647964","https://openalex.org/W2106251971","https://openalex.org/W2121169595","https://openalex.org/W2121711235","https://openalex.org/W2126823681","https://openalex.org/W2133916137","https://openalex.org/W2136257417","https://openalex.org/W2142659896","https://openalex.org/W2158881717","https://openalex.org/W2170009145","https://openalex.org/W6635247266","https://openalex.org/W6680543196"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2617666058","https://openalex.org/W2803012234","https://openalex.org/W2090213929","https://openalex.org/W2165139624","https://openalex.org/W3006003651","https://openalex.org/W2127892766","https://openalex.org/W2144282137"],"abstract_inverted_index":{"This":[0],"paper":[1],"introduces":[2],"a":[3,10,16,25,44,169],"methodology":[4],"that":[5,50,146],"optimizes":[6],"the":[7,28,52,56,61,72,84,107,110,129,147,162,175,180],"performance":[8],"of":[9,60,81,100,109,157,172,174],"low":[11,68,73,111,149],"swing":[12,69,112,150],"clock":[13,20,29,37,53,64,70,113,151,176],"tree":[14,152],"under":[15,55],"skew":[17,54,58,170,182],"bound.":[18],"Low-swing":[19],"trees":[21,114],"are":[22],"preferred":[23],"for":[24],"reduction":[26,160],"in":[27,36,103,115,161],"switching":[30],"power,":[31],"with":[32,119,128,165],"an":[33,155],"expected":[34],"trade-off":[35],"slew":[38,82],"and":[39,140],"skew.":[40],"In":[41,66],"this":[42,67],"paper,":[43],"heuristic":[45],"optimization":[46],"process":[47],"is":[48,77,88,95],"introduced":[49],"keeps":[51],"same":[57],"budget":[59],"originating":[62],"full-swing":[63],"tree.":[65],"optimization,":[71],"power":[74,117,163],"consumption":[75,118,164],"property":[76],"preserved.":[78],"The":[79,125],"effect":[80],"on":[83,122],"logic":[85],"timing,":[86],"which":[87],"naturally":[89],"degraded":[90],"due":[91],"to":[92,105],"low-swing":[93],"operation,":[94],"analyzed":[96],"within":[97,179],"timing":[98,123],"slack":[99],"some":[101],"paths":[102],"order":[104],"highlight":[106],"effectiveness":[108],"lowering":[116],"limited":[120],"impact":[121],"constraints.":[124],"experiments":[126],"performed":[127],"4":[130,141],"largest":[131],"ISCAS'89":[132],"benchmark":[133],"circuits":[134],"operating":[135],"at":[136],"500~MHz,":[137],"90~nm":[138],"technology":[139],"different":[142],"Vdd":[143],"levels":[144],"show":[145],"optimized":[148],"can":[153],"achieve":[154],"average":[156],"upto":[158],"11.0%":[159],"no":[166],"more":[167],"than":[168],"degradation":[171],"0.5%":[173],"period":[177],"(i.e.":[178],"practical":[181],"budget).":[183]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}