{"id":"https://openalex.org/W2019135189","doi":"https://doi.org/10.1145/2464996.2467285","title":"Network-on-chip for a partially reconfigurable FPGA system","display_name":"Network-on-chip for a partially reconfigurable FPGA system","publication_year":2013,"publication_date":"2013-05-28","ids":{"openalex":"https://openalex.org/W2019135189","doi":"https://doi.org/10.1145/2464996.2467285","mag":"2019135189"},"language":"en","primary_location":{"id":"doi:10.1145/2464996.2467285","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2464996.2467285","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 27th international ACM conference on International conference on supercomputing","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108090937","display_name":"Justin A. Hogan","orcid":null},"institutions":[{"id":"https://openalex.org/I23732399","display_name":"Montana State University","ror":"https://ror.org/02w0trx84","country_code":"US","type":"education","lineage":["https://openalex.org/I23732399","https://openalex.org/I4210126032"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Justin A. Hogan","raw_affiliation_strings":["Montana State University, Bozeman, MT, USA","Montana State University , Bozeman , MT , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Montana State University, Bozeman, MT, USA","institution_ids":["https://openalex.org/I23732399"]},{"raw_affiliation_string":"Montana State University , Bozeman , MT , USA","institution_ids":["https://openalex.org/I23732399"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049750668","display_name":"Raymond J. Weber","orcid":"https://orcid.org/0000-0002-4176-1493"},"institutions":[{"id":"https://openalex.org/I23732399","display_name":"Montana State University","ror":"https://ror.org/02w0trx84","country_code":"US","type":"education","lineage":["https://openalex.org/I23732399","https://openalex.org/I4210126032"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Raymond J. Weber","raw_affiliation_strings":["Montana State University, Bozeman, MT, USA","Montana State University , Bozeman , MT , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Montana State University, Bozeman, MT, USA","institution_ids":["https://openalex.org/I23732399"]},{"raw_affiliation_string":"Montana State University , Bozeman , MT , USA","institution_ids":["https://openalex.org/I23732399"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040593195","display_name":"Brock J. LaMeres","orcid":"https://orcid.org/0000-0001-9388-4092"},"institutions":[{"id":"https://openalex.org/I23732399","display_name":"Montana State University","ror":"https://ror.org/02w0trx84","country_code":"US","type":"education","lineage":["https://openalex.org/I23732399","https://openalex.org/I4210126032"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brock J. LaMeres","raw_affiliation_strings":["Montana State University, Bozeman, MT, USA","Montana State University , Bozeman , MT , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Montana State University, Bozeman, MT, USA","institution_ids":["https://openalex.org/I23732399"]},{"raw_affiliation_string":"Montana State University , Bozeman , MT , USA","institution_ids":["https://openalex.org/I23732399"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062842506","display_name":"Todd Kaiser","orcid":null},"institutions":[{"id":"https://openalex.org/I23732399","display_name":"Montana State University","ror":"https://ror.org/02w0trx84","country_code":"US","type":"education","lineage":["https://openalex.org/I23732399","https://openalex.org/I4210126032"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Todd Kaiser","raw_affiliation_strings":["Montana State University, Bozeman, MT, USA","Montana State University , Bozeman , MT , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Montana State University, Bozeman, MT, USA","institution_ids":["https://openalex.org/I23732399"]},{"raw_affiliation_string":"Montana State University , Bozeman , MT , USA","institution_ids":["https://openalex.org/I23732399"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I23732399"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"473","last_page":"474"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.991599977016449,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7665987014770508},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7408546209335327},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.7195466756820679},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.7064768671989441},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6969119906425476},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.6163483262062073},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.585780680179596},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5385658740997314},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5153428912162781},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.5072638392448425},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.48287561535835266},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.42426058650016785},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2531284689903259}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7665987014770508},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7408546209335327},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.7195466756820679},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.7064768671989441},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6969119906425476},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.6163483262062073},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.585780680179596},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5385658740997314},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5153428912162781},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.5072638392448425},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.48287561535835266},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.42426058650016785},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2531284689903259},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2464996.2467285","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2464996.2467285","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 27th international ACM conference on International conference on supercomputing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.49000000953674316,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2036681499","https://openalex.org/W4281711577","https://openalex.org/W2120080222","https://openalex.org/W2106200299","https://openalex.org/W2540211551","https://openalex.org/W2144357574","https://openalex.org/W1966325333","https://openalex.org/W3198758847","https://openalex.org/W3117657225","https://openalex.org/W4230458348"],"abstract_inverted_index":{"A":[0],"custom":[1],"FPGA-based,":[2],"1U":[3],"CubeSat":[4],"form-factor":[5],"reconfigurable":[6,54],"computing":[7],"development":[8],"platform":[9,27],"has":[10],"been":[11],"designed":[12,29],"and":[13,20,23,36,56],"built":[14],"for":[15,77],"the":[16,32,41],"purpose":[17],"of":[18,40],"implementing":[19],"testing":[21],"multicore":[22,79],"multiprocessor":[24],"systems.":[25],"The":[26],"was":[28],"to":[30],"leverage":[31],"active":[33],"partial":[34],"reconfiguration":[35],"configuration":[37],"readback":[38],"capabilities":[39],"Xilinx":[42],"Virtex-6":[43],"device.":[44],"This":[45],"enables":[46],"myriad":[47],"research":[48,73],"opportunities":[49],"in":[50],"parallel":[51],"processing,":[52],"high-performance":[53],"computing,":[55],"multicore/multiprocessor":[57],"system":[58,69,80],"design.":[59],"An":[60],"example":[61],"application":[62],"features":[63],"a":[64],"nine-processor":[65],"radiation":[66],"tolerant":[67],"computer":[68],"which":[70],"motivates":[71],"further":[72],"into":[74],"network-on-chip":[75],"solutions":[76],"reducing":[78],"routing":[81],"complexity.":[82]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
