{"id":"https://openalex.org/W1992200860","doi":"https://doi.org/10.1145/2463209.2488921","title":"Routability-driven placement for hierarchical mixed-size circuit designs","display_name":"Routability-driven placement for hierarchical mixed-size circuit designs","publication_year":2013,"publication_date":"2013-05-28","ids":{"openalex":"https://openalex.org/W1992200860","doi":"https://doi.org/10.1145/2463209.2488921","mag":"1992200860"},"language":"en","primary_location":{"id":"doi:10.1145/2463209.2488921","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2463209.2488921","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 50th Annual Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5114202908","display_name":"Meng-Kai Hsu","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Meng-Kai Hsu","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan","Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan#TAB#"],"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan#TAB#","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100702303","display_name":"Yifang Chen","orcid":"https://orcid.org/0000-0002-4135-5508"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yi-Fang Chen","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan","Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan#TAB#"],"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan#TAB#","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032624921","display_name":"Chau-Chin Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chau-Chin Huang","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan","Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan#TAB#"],"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan#TAB#","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089860877","display_name":"Tung-Chieh Chen","orcid":"https://orcid.org/0009-0000-3163-3634"},"institutions":[{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Tung-Chieh Chen","raw_affiliation_strings":["Synopsys Inc., Hsinchu, Taiwan","[Synopsys Inc., Hsinchu, Taiwan]"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc., Hsinchu, Taiwan","institution_ids":[]},{"raw_affiliation_string":"[Synopsys Inc., Hsinchu, Taiwan]","institution_ids":["https://openalex.org/I1335490905"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018371636","display_name":"Yao\u2010Wen Chang","orcid":"https://orcid.org/0000-0002-0564-5719"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yao-Wen Chang","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan","Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan#TAB#"],"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan#TAB#","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5114202908"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":4.4926,"has_fulltext":false,"cited_by_count":37,"citation_normalized_percentile":{"value":0.94838665,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7029430270195007},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5545048713684082},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.5374577045440674},{"id":"https://openalex.org/keywords/placer-mining","display_name":"Placer mining","score":0.5301051139831543},{"id":"https://openalex.org/keywords/turnaround-time","display_name":"Turnaround time","score":0.4782741963863373},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.46669939160346985},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.46485769748687744},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.46125754714012146},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.441700279712677},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.42756664752960205},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.42086225748062134},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.3510848879814148},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2742331326007843},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2632300853729248}],"concepts":[{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7029430270195007},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5545048713684082},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.5374577045440674},{"id":"https://openalex.org/C43592290","wikidata":"https://www.wikidata.org/wiki/Q12148490","display_name":"Placer mining","level":2,"score":0.5301051139831543},{"id":"https://openalex.org/C176553487","wikidata":"https://www.wikidata.org/wiki/Q7855819","display_name":"Turnaround time","level":2,"score":0.4782741963863373},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.46669939160346985},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.46485769748687744},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.46125754714012146},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.441700279712677},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.42756664752960205},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.42086225748062134},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3510848879814148},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2742331326007843},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2632300853729248},{"id":"https://openalex.org/C191897082","wikidata":"https://www.wikidata.org/wiki/Q11467","display_name":"Metallurgy","level":1,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2463209.2488921","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2463209.2488921","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 50th Annual Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1971840653","https://openalex.org/W2008934489","https://openalex.org/W2011912079","https://openalex.org/W2018351041","https://openalex.org/W2022844803","https://openalex.org/W2058324481","https://openalex.org/W2059199163","https://openalex.org/W2072175262","https://openalex.org/W2085456403","https://openalex.org/W2097189804","https://openalex.org/W2099184857","https://openalex.org/W2099223028","https://openalex.org/W2117278010","https://openalex.org/W2133367791","https://openalex.org/W2144642377","https://openalex.org/W2149625434","https://openalex.org/W2167190617","https://openalex.org/W2170957689","https://openalex.org/W2173598676","https://openalex.org/W2178255440","https://openalex.org/W3151205559","https://openalex.org/W4240744150","https://openalex.org/W6681942916","https://openalex.org/W6981165577"],"related_works":["https://openalex.org/W2156550631","https://openalex.org/W2155675690","https://openalex.org/W1563562883","https://openalex.org/W2185927297","https://openalex.org/W2111591643","https://openalex.org/W2163932442","https://openalex.org/W2030852227","https://openalex.org/W3151104204","https://openalex.org/W2391887037","https://openalex.org/W2102676394"],"abstract_inverted_index":{"A":[0],"wirelength-driven":[1],"placer":[2,20,84],"without":[3],"considering":[4,103],"routability":[5,56],"could":[6],"introduce":[7],"irresolvable":[8],"routing-congested":[9],"placements.":[10],"Therefore,":[11],"it":[12],"is":[13,65],"desirable":[14],"to":[15,39],"develop":[16],"an":[17],"effective":[18],"routability-driven":[19],"for":[21,28,47,73],"modern":[22],"mixed-size":[23],"designs":[24],"employing":[25],"hierarchical":[26],"methodologies":[27],"faster":[29],"turnaround":[30],"time.":[31],"This":[32],"paper":[33],"presents":[34],"a":[35,60],"novel":[36],"two-stage":[37],"technique":[38,64],"effectively":[40],"identify":[41],"design":[42],"hierarchies":[43],"and":[44,50,55,94,96],"guide":[45],"placement":[46],"better":[48],"wirelength":[49,54],"routability.":[51],"To":[52],"optimize":[53],"simultaneously":[57],"during":[58],"placement,":[59],"new":[61],"analytical":[62],"net-congestion-optimization":[63],"also":[66],"proposed.":[67],"Compared":[68],"with":[69],"the":[70,74,87,91,97],"participating":[71],"teams":[72],"2012":[75],"ICCAD":[76],"Design":[77],"Hierarchy":[78],"Aware":[79],"Routability-driven":[80],"Placement":[81],"Contest,":[82],"our":[83],"can":[85],"achieve":[86],"best":[88,98],"quality":[89],"(both":[90],"average":[92],"overflow":[93],"wire-length)":[95],"overall":[99],"score":[100],"(by":[101],"additionally":[102],"running":[104],"time).":[105]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":7},{"year":2014,"cited_by_count":8},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}