{"id":"https://openalex.org/W2135332296","doi":"https://doi.org/10.1145/2463209.2488874","title":"Dynamic voltage and frequency scaling for shared resources in multicore processor designs","display_name":"Dynamic voltage and frequency scaling for shared resources in multicore processor designs","publication_year":2013,"publication_date":"2013-05-28","ids":{"openalex":"https://openalex.org/W2135332296","doi":"https://doi.org/10.1145/2463209.2488874","mag":"2135332296"},"language":"en","primary_location":{"id":"doi:10.1145/2463209.2488874","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2463209.2488874","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 50th Annual Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100329931","display_name":"Xi Chen","orcid":"https://orcid.org/0000-0002-3135-4114"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Xi Chen","raw_affiliation_strings":["Texas A&M University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&M University","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101651955","display_name":"Zheng Xu","orcid":"https://orcid.org/0009-0003-6747-3953"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zheng Xu","raw_affiliation_strings":["Texas A&M University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&M University","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100388393","display_name":"Hyungjun Kim","orcid":"https://orcid.org/0009-0003-5078-4405"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hyungjun Kim","raw_affiliation_strings":["Texas A&M University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&M University","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082578661","display_name":"Paul V. Gratz","orcid":"https://orcid.org/0000-0001-7120-7189"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Paul V. Gratz","raw_affiliation_strings":["Texas A&M University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&M University","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103246390","display_name":"Jiang Hu","orcid":"https://orcid.org/0000-0003-1157-7799"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jiang Hu","raw_affiliation_strings":["Texas A&M University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&M University","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007256099","display_name":"Michael Kishinevsky","orcid":"https://orcid.org/0000-0002-5593-9694"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Michael Kishinevsky","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084255924","display_name":"\u00dcmit Y. Ogras","orcid":"https://orcid.org/0000-0002-5045-5535"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Umit Ogras","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078114699","display_name":"Raid Ayoub","orcid":"https://orcid.org/0000-0002-1175-2983"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Raid Ayoub","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":6.3433,"has_fulltext":false,"cited_by_count":63,"citation_normalized_percentile":{"value":0.96658629,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/frequency-scaling","display_name":"Frequency scaling","score":0.7739745378494263},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7319163084030151},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.7137962579727173},{"id":"https://openalex.org/keywords/parsec","display_name":"Parsec","score":0.6171474456787109},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6084316372871399},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5256335139274597},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.47981905937194824},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4762725234031677},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.4689618647098541},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4682389795780182},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.42377007007598877},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40225017070770264},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3908163607120514},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1436309814453125},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13986358046531677},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12143877148628235}],"concepts":[{"id":"https://openalex.org/C157742956","wikidata":"https://www.wikidata.org/wiki/Q3237776","display_name":"Frequency scaling","level":3,"score":0.7739745378494263},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7319163084030151},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.7137962579727173},{"id":"https://openalex.org/C44060867","wikidata":"https://www.wikidata.org/wiki/Q12129","display_name":"Parsec","level":3,"score":0.6171474456787109},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6084316372871399},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5256335139274597},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.47981905937194824},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4762725234031677},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.4689618647098541},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4682389795780182},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.42377007007598877},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40225017070770264},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3908163607120514},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1436309814453125},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13986358046531677},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12143877148628235},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C150846664","wikidata":"https://www.wikidata.org/wiki/Q7602306","display_name":"Stars","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2463209.2488874","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2463209.2488874","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 50th Annual Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8600000143051147,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1833719054","https://openalex.org/W1980699667","https://openalex.org/W1981750308","https://openalex.org/W2018537611","https://openalex.org/W2077505860","https://openalex.org/W2080418535","https://openalex.org/W2093411808","https://openalex.org/W2103028594","https://openalex.org/W2109681980","https://openalex.org/W2112704250","https://openalex.org/W2128398793","https://openalex.org/W2131054871","https://openalex.org/W2147657366","https://openalex.org/W2158684546","https://openalex.org/W2166834317","https://openalex.org/W2169875292","https://openalex.org/W2182414722","https://openalex.org/W2232152497","https://openalex.org/W2464177207"],"related_works":["https://openalex.org/W2154351074","https://openalex.org/W2151223307","https://openalex.org/W2071013889","https://openalex.org/W2023400509","https://openalex.org/W2332054630","https://openalex.org/W2590100594","https://openalex.org/W2154169726","https://openalex.org/W2792585858","https://openalex.org/W2188576602","https://openalex.org/W3092052573"],"abstract_inverted_index":{"As":[0],"the":[1,10,52,76],"core":[2],"count":[3],"in":[4,47],"processor":[5,49],"chips":[6],"grows,":[7],"so":[8],"do":[9],"on-die,":[11],"shared":[12,20,53],"resources":[13,54],"such":[14],"as":[15],"on-chip":[16],"communication":[17],"fabric":[18],"and":[19,30,43,65,69],"cache,":[21],"which":[22],"are":[23,67],"of":[24,41],"paramount":[25],"importance":[26],"for":[27,37,63],"chip":[28],"performance":[29],"power.":[31],"This":[32],"paper":[33],"presents":[34],"a":[35,56,88],"method":[36],"dynamic":[38],"voltage/frequency":[39,58],"scaling":[40],"networks-on-chip":[42],"last":[44],"level":[45],"caches":[46],"multicore":[48],"designs,":[50],"where":[51],"form":[55],"single":[57],"domain.":[59],"Several":[60],"new":[61],"techniques":[62,80],"monitoring":[64],"control":[66],"developed,":[68],"validated":[70],"through":[71],"full":[72],"system":[73],"simulations":[74],"on":[75],"PARSEC":[77],"benchmarks.":[78],"These":[79],"reduce":[81],"energy-delay":[82],"product":[83],"by":[84],"56%":[85],"compared":[86],"to":[87],"state-of-the-art":[89],"prior":[90],"work.":[91]},"counts_by_year":[{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":11},{"year":2017,"cited_by_count":18},{"year":2016,"cited_by_count":8},{"year":2015,"cited_by_count":7},{"year":2014,"cited_by_count":5}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}