{"id":"https://openalex.org/W2167872527","doi":"https://doi.org/10.1145/2463209.2488871","title":"Relax-and-retime","display_name":"Relax-and-retime","publication_year":2013,"publication_date":"2013-05-28","ids":{"openalex":"https://openalex.org/W2167872527","doi":"https://doi.org/10.1145/2463209.2488871","mag":"2167872527"},"language":"en","primary_location":{"id":"doi:10.1145/2463209.2488871","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2463209.2488871","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 50th Annual Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033127135","display_name":"Shankar Ganesh Ramasubramanian","orcid":"https://orcid.org/0000-0003-3938-9052"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Shankar Ganesh Ramasubramanian","raw_affiliation_strings":["Purdue University"],"affiliations":[{"raw_affiliation_string":"Purdue University","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010094713","display_name":"Swagath Venkataramani","orcid":"https://orcid.org/0000-0002-0470-6364"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Swagath Venkataramani","raw_affiliation_strings":["Purdue University"],"affiliations":[{"raw_affiliation_string":"Purdue University","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001319730","display_name":"Adithya Parandhaman","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Adithya Parandhaman","raw_affiliation_strings":["Purdue University"],"affiliations":[{"raw_affiliation_string":"Purdue University","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065766721","display_name":"Anand Raghunathan","orcid":"https://orcid.org/0000-0002-4624-564X"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anand Raghunathan","raw_affiliation_strings":["Purdue University"],"affiliations":[{"raw_affiliation_string":"Purdue University","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5033127135"],"corresponding_institution_ids":["https://openalex.org/I219193219"],"apc_list":null,"apc_paid":null,"fwci":3.7832,"has_fulltext":false,"cited_by_count":32,"citation_normalized_percentile":{"value":0.93939662,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.7693318128585815},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6776023507118225},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.5646708011627197},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5428197383880615},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.5418643951416016},{"id":"https://openalex.org/keywords/guard","display_name":"Guard (computer science)","score":0.5057189464569092},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4946734607219696},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4872190058231354},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47167453169822693},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4626060426235199},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.4536149501800537},{"id":"https://openalex.org/keywords/structuring","display_name":"Structuring","score":0.44248050451278687},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4269729256629944},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3537523150444031},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2760167717933655},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18710774183273315},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1611124873161316},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.1352132260799408}],"concepts":[{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.7693318128585815},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6776023507118225},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.5646708011627197},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5428197383880615},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.5418643951416016},{"id":"https://openalex.org/C141141315","wikidata":"https://www.wikidata.org/wiki/Q2379942","display_name":"Guard (computer science)","level":2,"score":0.5057189464569092},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4946734607219696},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4872190058231354},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47167453169822693},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4626060426235199},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.4536149501800537},{"id":"https://openalex.org/C2775945657","wikidata":"https://www.wikidata.org/wiki/Q381442","display_name":"Structuring","level":2,"score":0.44248050451278687},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4269729256629944},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3537523150444031},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2760167717933655},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18710774183273315},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1611124873161316},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.1352132260799408},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2463209.2488871","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2463209.2488871","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 50th Annual Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.9100000262260437,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W2059802459","https://openalex.org/W2078866603","https://openalex.org/W2082568343","https://openalex.org/W2087656024","https://openalex.org/W2098764315","https://openalex.org/W2100995829","https://openalex.org/W2104677471","https://openalex.org/W2110283673","https://openalex.org/W2111485030","https://openalex.org/W2119422129","https://openalex.org/W2124429975","https://openalex.org/W2135174628","https://openalex.org/W2151802820","https://openalex.org/W2163421219","https://openalex.org/W2170018982","https://openalex.org/W2171577385"],"related_works":["https://openalex.org/W2110968362","https://openalex.org/W4238178324","https://openalex.org/W2163776294","https://openalex.org/W3141297747","https://openalex.org/W4248668797","https://openalex.org/W2111485030","https://openalex.org/W818963952","https://openalex.org/W1939541994","https://openalex.org/W1851795671","https://openalex.org/W2146663621"],"abstract_inverted_index":{"Recovery":[0],"based":[1],"design":[2,10,33,65],"(RBD)":[3],"is":[4,62],"a":[5,43,87],"promising":[6],"approach":[7],"for":[8],"the":[9,57,81,116,126,131,135,138],"of":[11,60,83,107,130,137],"energy-efficient":[12],"circuits":[13,18,72],"under":[14,50],"variations.":[15],"RBD":[16,37,61],"instruments":[17],"with":[19,73],"mechanisms":[20],"to":[21,42,56,77,113],"identify":[22],"and":[23,67],"correct":[24],"timing":[25,46,84],"violations,":[26],"thereby":[27],"allowing":[28],"reduced":[29],"guard":[30],"bands":[31],"or":[32],"margins.":[34],"In":[35],"addition,":[36],"enables":[38],"aggressive":[39],"voltage":[40],"overscaling":[41],"point":[44],"where":[45],"errors":[47,85],"occur":[48],"even":[49],"nominal":[51],"conditions.":[52],"A":[53],"major":[54],"barrier":[55],"widespread":[58],"adoption":[59],"that":[63],"traditional":[64],"practices":[66],"synthesis":[68],"tools":[69],"result":[70],"in":[71,80],"so-called\"path":[74],"walls\",":[75],"leading":[76],"an":[78],"explosion":[79],"number":[82],"beyond":[86],"certain":[88],"critical":[89],"operating":[90],"voltage.":[91],"To":[92],"alleviate":[93],"this":[94],"effect,":[95],"previous":[96],"techniques":[97,122],"focused":[98],"on":[99],"combinational":[100,139],"circuit":[101],"optimizations":[102],"such":[103],"as":[104],"sizing,":[105],"use":[106],"dual":[108],"Vth":[109],"cells,":[110],"re-structuring,":[111],"etc.":[112],"favorably":[114],"reshape":[115],"path":[117],"delay":[118],"distribution.":[119],"However,":[120],"these":[121],"are":[123],"limited":[124],"by":[125],"inherent":[127],"sequential":[128],"structure":[129],"circuit,":[132],"which":[133],"defines":[134],"boundaries":[136],"logic.":[140]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":8},{"year":2015,"cited_by_count":7},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}