{"id":"https://openalex.org/W2154302973","doi":"https://doi.org/10.1145/2463209.2488746","title":"An efficient and effective analytical placer for FPGAs","display_name":"An efficient and effective analytical placer for FPGAs","publication_year":2013,"publication_date":"2013-05-28","ids":{"openalex":"https://openalex.org/W2154302973","doi":"https://doi.org/10.1145/2463209.2488746","mag":"2154302973"},"language":"en","primary_location":{"id":"doi:10.1145/2463209.2488746","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2463209.2488746","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 50th Annual Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001086483","display_name":"Tzu-Hen Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Tzu-Hen Lin","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106232660","display_name":"P. Banerjee","orcid":"https://orcid.org/0009-0005-3184-6871"},"institutions":[{"id":"https://openalex.org/I106542073","display_name":"University of Calcutta","ror":"https://ror.org/01e7v7w47","country_code":"IN","type":"education","lineage":["https://openalex.org/I106542073"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pritha Banerjee","raw_affiliation_strings":["University of Calcutta, Kolkata, West Bengal, IN"],"affiliations":[{"raw_affiliation_string":"University of Calcutta, Kolkata, West Bengal, IN","institution_ids":["https://openalex.org/I106542073"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018371636","display_name":"Yao\u2010Wen Chang","orcid":"https://orcid.org/0000-0002-0564-5719"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yao-Wen Chang","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5001086483"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":3.3103,"has_fulltext":false,"cited_by_count":46,"citation_normalized_percentile":{"value":0.92861573,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7860504388809204},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.7701669931411743},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7322907447814941},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7027735114097595},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.6396916508674622},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6340739130973816},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.5361485481262207},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4894934892654419},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3297157883644104},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.324685275554657},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3042336106300354},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2481774389743805},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.23755866289138794},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2211277186870575},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10405763983726501}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7860504388809204},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.7701669931411743},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7322907447814941},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7027735114097595},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.6396916508674622},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6340739130973816},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.5361485481262207},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4894934892654419},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3297157883644104},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.324685275554657},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3042336106300354},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2481774389743805},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.23755866289138794},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2211277186870575},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10405763983726501},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2463209.2488746","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2463209.2488746","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 50th Annual Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Peace, Justice and strong institutions","score":0.7200000286102295,"id":"https://metadata.un.org/sdg/16"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1984954427","https://openalex.org/W1996746141","https://openalex.org/W2014316444","https://openalex.org/W2023788229","https://openalex.org/W2035847677","https://openalex.org/W2041941568","https://openalex.org/W2075137913","https://openalex.org/W2094806828","https://openalex.org/W2111104699","https://openalex.org/W2111756578","https://openalex.org/W2114871550","https://openalex.org/W2138206217","https://openalex.org/W2139637699","https://openalex.org/W2154014710","https://openalex.org/W2158961316","https://openalex.org/W2162141797","https://openalex.org/W2167190617","https://openalex.org/W2736309523","https://openalex.org/W6680484343"],"related_works":["https://openalex.org/W3183044703","https://openalex.org/W1875577501","https://openalex.org/W1968931833","https://openalex.org/W4245174233","https://openalex.org/W2122425352","https://openalex.org/W108855261","https://openalex.org/W2098132017","https://openalex.org/W4244167835","https://openalex.org/W2031837447","https://openalex.org/W4213145382"],"abstract_inverted_index":{"The":[0],"increasing":[1],"design":[2],"complexity":[3],"of":[4,49],"modern":[5],"circuits":[6],"has":[7],"made":[8],"traditional":[9],"FPGA":[10,21,109],"placement":[11,22,41,55],"techniques":[12],"not":[13],"efficient":[14],"anymore.":[15],"To":[16],"improve":[17],"the":[18,35,57,104],"scalability,":[19],"commercial":[20],"tools":[23],"have":[24],"started":[25],"migrating":[26],"to":[27,102],"analytical":[28,40,53],"placement.":[29,76],"In":[30],"this":[31],"paper,":[32],"we":[33],"propose":[34],"first":[36],"academic":[37,107],"multilevel":[38,51],"timing-and-wirelength-driven":[39,52],"algorithm":[42,47],"for":[43],"FPGAs.":[44],"Our":[45],"proposed":[46,82],"consists":[48],"(1)":[50],"global":[54],"with":[56,90],"novel":[58],"block":[59,67],"alignment":[60],"consideration,":[61],"(2)":[62],"partitioning-based":[63],"legalization,":[64],"(3)":[65],"wirelength-driven":[66],"matching-based":[68],"detailed":[69,75],"placement,":[70],"and":[71,96],"(4)":[72],"timing-driven":[73],"simulated-annealing-based":[74,108],"Experimental":[77],"results":[78],"show":[79],"that":[80],"our":[81],"approach":[83],"can":[84],"achieve":[85],"6.91x":[86],"speedup":[87],"on":[88],"average":[89],"7%":[91],"smaller":[92],"critical":[93],"path":[94],"delay":[95],"1%":[97],"shorter":[98],"routed":[99],"wirelength":[100],"compared":[101],"VPR,":[103],"well-known,":[105],"state-of-the-art":[106],"placer.":[110]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":12},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
