{"id":"https://openalex.org/W2051392577","doi":"https://doi.org/10.1145/2460216.2460227","title":"Energy-efficient dataflow computations on FPGAs using application-specific coarse-grain architecture synthesis","display_name":"Energy-efficient dataflow computations on FPGAs using application-specific coarse-grain architecture synthesis","publication_year":2012,"publication_date":"2012-03-25","ids":{"openalex":"https://openalex.org/W2051392577","doi":"https://doi.org/10.1145/2460216.2460227","mag":"2051392577"},"language":"en","primary_location":{"id":"doi:10.1145/2460216.2460227","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2460216.2460227","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037721813","display_name":"Colin Yu Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I889458895","display_name":"University of Hong Kong","ror":"https://ror.org/02zhqgq86","country_code":"HK","type":"education","lineage":["https://openalex.org/I889458895"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Colin Yu Lin","raw_affiliation_strings":["The University of Hong Kong"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Hong Kong","institution_ids":["https://openalex.org/I889458895"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020581824","display_name":"Hayden Kwok\u2010Hay So","orcid":"https://orcid.org/0000-0002-6514-0237"},"institutions":[{"id":"https://openalex.org/I889458895","display_name":"University of Hong Kong","ror":"https://ror.org/02zhqgq86","country_code":"HK","type":"education","lineage":["https://openalex.org/I889458895"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Hayden Kwok-Hay Kwok-Hay So","raw_affiliation_strings":["The University of Hong Kong"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Hong Kong","institution_ids":["https://openalex.org/I889458895"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I889458895"],"apc_list":null,"apc_paid":null,"fwci":0.869,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.73655964,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"40","issue":"5","first_page":"58","last_page":"63"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.9325897693634033},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8206031322479248},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7387353181838989},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.640244722366333},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5711285471916199},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5567585229873657},{"id":"https://openalex.org/keywords/dataflow-architecture","display_name":"Dataflow architecture","score":0.5133025050163269},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.5077224969863892},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.48281463980674744},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.47492557764053345},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.47202959656715393},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46521854400634766},{"id":"https://openalex.org/keywords/compile-time","display_name":"Compile time","score":0.4519854784011841},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.44925010204315186},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11696559190750122},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09907025098800659}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.9325897693634033},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8206031322479248},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7387353181838989},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.640244722366333},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5711285471916199},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5567585229873657},{"id":"https://openalex.org/C176727019","wikidata":"https://www.wikidata.org/wiki/Q1172415","display_name":"Dataflow architecture","level":3,"score":0.5133025050163269},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.5077224969863892},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.48281463980674744},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.47492557764053345},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.47202959656715393},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46521854400634766},{"id":"https://openalex.org/C200833197","wikidata":"https://www.wikidata.org/wiki/Q333707","display_name":"Compile time","level":3,"score":0.4519854784011841},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.44925010204315186},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11696559190750122},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09907025098800659},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2460216.2460227","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2460216.2460227","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8600000143051147,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2019388247","https://openalex.org/W2122867301","https://openalex.org/W2143714984","https://openalex.org/W2156420848","https://openalex.org/W2160126455"],"related_works":["https://openalex.org/W1557107163","https://openalex.org/W2356029519","https://openalex.org/W1601646354","https://openalex.org/W157064208","https://openalex.org/W2078700326","https://openalex.org/W4320854292","https://openalex.org/W3003815297","https://openalex.org/W2461217932","https://openalex.org/W2887983008","https://openalex.org/W1998888015"],"abstract_inverted_index":{"Compiling":[0],"high-level":[1,163,180],"user":[2],"applications":[3],"to":[4,70,77,99,153,159,174],"execute":[5],"on":[6,35,54,66],"FPGAbased":[7],"reconfigurable":[8],"computers":[9],"often":[10],"involve":[11,115],"synthesizing":[12],"dataflow":[13,33],"graphs":[14,34],"beyond":[15],"the":[16,19,51,55,58,62,72,78,85,106,117,131,135,148],"capacity":[17],"of":[18,31,40,50,80,87,119,169,178],"available":[20],"hardware":[21],"resources.":[22],"A":[23],"framework":[24,150,171],"that":[25],"provides":[26],"rapid":[27],"and":[28,57,130,142,144],"energyefficient":[29],"compilation":[30],"such":[32,170],"FPGAs":[36],"using":[37],"an":[38,88],"array":[39],"pre-placed":[41],"configurable":[42],"processing":[43],"elements":[44],"is":[45,125,172],"proposed.":[46],"The":[47,167],"mapping":[48,143],"schedule":[49],"compute":[52],"operations":[53],"CPEs":[56,63,107],"direct":[59],"network":[60],"among":[61,134],"are":[64,108],"co-synthesized":[65],"a":[67,81,93,112,120,160,179],"per-application":[68],"basis":[69],"provide":[71],"targeted":[73],"power-performance":[74],"tradeoff.":[75],"Compared":[76],"use":[79,86,168],"fixed":[82],"generic":[83],"topology,":[84],"application-specific":[89,145],"topology":[90],"derived":[91],"by":[92],"genetic":[94],"algorithm":[95],"can":[96],"achieve":[97],"up":[98,152],"28%":[100],"improvement":[101],"in":[102,127,139],"energy-delay":[103,156],"product.":[104],"As":[105],"pre-placed,":[109],"compiling":[110],"for":[111,183],"new":[113,121,132],"application":[114,181],"only":[116],"generation":[118],"operation":[122,140],"schedule,":[123],"which":[124],"stored":[126],"on-chip":[128],"memory,":[129],"routes":[133],"CPEs.":[136],"With":[137],"optimization":[138],"scheduling":[141],"interconnect":[146],"network,":[147],"proposed":[149],"achieved":[151],"199X":[154],"better":[155],"product":[157],"compared":[158],"traditional":[161],"FPGA":[162],"synthesis":[164],"tool":[165],"xPilot.":[166],"anticipated":[173],"serve":[175],"as":[176],"part":[177],"compiler":[182],"hybrid":[184],"CPU-FPGA":[185],"computation.":[186]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":6},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}