{"id":"https://openalex.org/W2016931788","doi":"https://doi.org/10.1145/2458523.2458535","title":"Fast dynamic memory allocator for massively parallel architectures","display_name":"Fast dynamic memory allocator for massively parallel architectures","publication_year":2013,"publication_date":"2013-03-16","ids":{"openalex":"https://openalex.org/W2016931788","doi":"https://doi.org/10.1145/2458523.2458535","mag":"2016931788"},"language":"en","primary_location":{"id":"doi:10.1145/2458523.2458535","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2458523.2458535","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 6th Workshop on General Purpose Processor Using Graphics Processing Units","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109035226","display_name":"Sven Widmer","orcid":null},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Sven Widmer","raw_affiliation_strings":["Graduate School Computational Engineering, TU Darmstadt"],"affiliations":[{"raw_affiliation_string":"Graduate School Computational Engineering, TU Darmstadt","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017560407","display_name":"Dominik Wodniok","orcid":null},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Dominik Wodniok","raw_affiliation_strings":["Graduate School Computational Engineering, TU Darmstadt"],"affiliations":[{"raw_affiliation_string":"Graduate School Computational Engineering, TU Darmstadt","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110023001","display_name":"Nicolas Weber","orcid":"https://orcid.org/0000-0003-0032-9511"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Nicolas Weber","raw_affiliation_strings":["TU Darmstadt"],"affiliations":[{"raw_affiliation_string":"TU Darmstadt","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066521879","display_name":"Michael Goesele","orcid":"https://orcid.org/0000-0002-0944-0980"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Michael Goesele","raw_affiliation_strings":["Graduate School Computational Engineering, TU Darmstadt"],"affiliations":[{"raw_affiliation_string":"Graduate School Computational Engineering, TU Darmstadt","institution_ids":["https://openalex.org/I31512782"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5109035226"],"corresponding_institution_ids":["https://openalex.org/I31512782"],"apc_list":null,"apc_paid":null,"fwci":4.1147,"has_fulltext":false,"cited_by_count":30,"citation_normalized_percentile":{"value":0.93884582,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"120","last_page":"126"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8623377084732056},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.8377500772476196},{"id":"https://openalex.org/keywords/massively-parallel","display_name":"Massively parallel","score":0.8336384296417236},{"id":"https://openalex.org/keywords/allocator","display_name":"Allocator","score":0.7340164184570312},{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.7084444761276245},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.6905125975608826},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.6430298686027527},{"id":"https://openalex.org/keywords/c-dynamic-memory-allocation","display_name":"C dynamic memory allocation","score":0.4657600224018097},{"id":"https://openalex.org/keywords/cuda","display_name":"CUDA","score":0.4462757706642151},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3809354901313782},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.14551296830177307}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8623377084732056},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.8377500772476196},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.8336384296417236},{"id":"https://openalex.org/C162262903","wikidata":"https://www.wikidata.org/wiki/Q343527","display_name":"Allocator","level":2,"score":0.7340164184570312},{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.7084444761276245},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.6905125975608826},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.6430298686027527},{"id":"https://openalex.org/C34339311","wikidata":"https://www.wikidata.org/wiki/Q1050390","display_name":"C dynamic memory allocation","level":4,"score":0.4657600224018097},{"id":"https://openalex.org/C2778119891","wikidata":"https://www.wikidata.org/wiki/Q477690","display_name":"CUDA","level":2,"score":0.4462757706642151},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3809354901313782},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.14551296830177307},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/2458523.2458535","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2458523.2458535","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 6th Workshop on General Purpose Processor Using Graphics Processing Units","raw_type":"proceedings-article"},{"id":"pmh:oai:tubiblio.ulb.tu-darmstadt.de:82622","is_oa":false,"landing_page_url":"http://doi.acm.org/10.1145/2458523.2458535","pdf_url":null,"source":{"id":"https://openalex.org/S4377196390","display_name":"TUbilio (Technical University of Darmstadt)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I31512782","host_organization_name":"Technische Universit\u00e4t Darmstadt","host_organization_lineage":["https://openalex.org/I31512782"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Konferenzver\u00f6ffentlichung"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320323384","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1852259245","https://openalex.org/W1899349177","https://openalex.org/W1916709771","https://openalex.org/W1983540755","https://openalex.org/W1989300723","https://openalex.org/W1993449345","https://openalex.org/W2014665656","https://openalex.org/W2039820867","https://openalex.org/W2128274900","https://openalex.org/W2136994812","https://openalex.org/W2752853835","https://openalex.org/W3128608526","https://openalex.org/W6640015234","https://openalex.org/W7054846718"],"related_works":["https://openalex.org/W2613115449","https://openalex.org/W4312275919","https://openalex.org/W2614685449","https://openalex.org/W2289703295","https://openalex.org/W2016931788","https://openalex.org/W2944623006","https://openalex.org/W4289363007","https://openalex.org/W1983540755","https://openalex.org/W2965005859","https://openalex.org/W2898191381"],"abstract_inverted_index":{"Dynamic":[0],"memory":[1,61],"allocation":[2,25],"in":[3,30,48],"massively":[4,51],"parallel":[5,52,67],"systems":[6],"often":[7],"suffers":[8],"from":[9],"drastic":[10],"performance":[11],"decreases":[12],"due":[13],"to":[14,36,91,115],"the":[15,44,65,94],"required":[16],"global":[17],"synchronization.":[18],"This":[19],"is":[20],"especially":[21],"true":[22],"when":[23],"many":[24],"or":[26],"deallocation":[27],"requests":[28],"occur":[29],"parallel.":[31],"We":[32,97],"propose":[33,57],"a":[34,58,78,101],"method":[35],"alleviate":[37],"this":[38],"problem":[39],"by":[40],"making":[41],"use":[42],"of":[43,81,113,118],"SIMD":[45,66],"parallelism":[46],"found":[47],"most":[49],"current":[50],"hardware.":[53],"More":[54],"specifically,":[55],"we":[56,88],"hybrid":[59],"dynamic":[60,95],"allocator":[62],"operating":[63],"at":[64],"warp":[68],"level.":[69],"Using":[70],"additional":[71],"constraints":[72],"that":[73],"can":[74],"be":[75],"fulfilled":[76],"for":[77,104],"large":[79],"class":[80],"practically":[82],"relevant":[83],"algorithms":[84],"and":[85,99],"hardware":[86],"systems,":[87],"are":[89],"able":[90],"significantly":[92],"speed-up":[93],"allocation.":[96],"present":[98],"evaluate":[100],"prototypical":[102],"implementation":[103],"modern":[105],"CUDA-enabled":[106],"graphics":[107],"cards,":[108],"achieving":[109],"an":[110],"overall":[111],"speedup":[112],"up":[114],"several":[116],"orders":[117],"magnitude.":[119]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":4},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":6}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}