{"id":"https://openalex.org/W1973131176","doi":"https://doi.org/10.1145/2435264.2435337","title":"Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only)","display_name":"Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only)","publication_year":2013,"publication_date":"2013-02-11","ids":{"openalex":"https://openalex.org/W1973131176","doi":"https://doi.org/10.1145/2435264.2435337","mag":"1973131176"},"language":"en","primary_location":{"id":"doi:10.1145/2435264.2435337","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2435264.2435337","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010288304","display_name":"Marc-Andr\u00e9 Daigneault","orcid":null},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Marc-Andre Daigneault","raw_affiliation_strings":["Ecole Polytechnique de Montreal, Montreal, Canada","Ecole Polytechnique de Montreal , Montreal , Canada"],"affiliations":[{"raw_affiliation_string":"Ecole Polytechnique de Montreal, Montreal, Canada","institution_ids":["https://openalex.org/I45683168"]},{"raw_affiliation_string":"Ecole Polytechnique de Montreal , Montreal , Canada","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067086966","display_name":"Jean\u2010Pierre David","orcid":"https://orcid.org/0000-0002-7707-0483"},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jean Pierre David","raw_affiliation_strings":["Ecole Polytechnique de Montreal, Montreal, Canada","Ecole Polytechnique de Montreal , Montreal , Canada"],"affiliations":[{"raw_affiliation_string":"Ecole Polytechnique de Montreal, Montreal, Canada","institution_ids":["https://openalex.org/I45683168"]},{"raw_affiliation_string":"Ecole Polytechnique de Montreal , Montreal , Canada","institution_ids":["https://openalex.org/I45683168"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5010288304"],"corresponding_institution_ids":["https://openalex.org/I45683168"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05806058,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"274","last_page":"275"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8708698153495789},{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.6381396651268005},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6258558034896851},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5167964696884155},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.42424753308296204},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4049603044986725},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38498371839523315},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37783992290496826},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3513186573982239}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8708698153495789},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.6381396651268005},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6258558034896851},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5167964696884155},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.42424753308296204},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4049603044986725},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38498371839523315},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37783992290496826},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3513186573982239},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/2435264.2435337","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2435264.2435337","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:publications.polymtl.ca:39629","is_oa":false,"landing_page_url":"https://publications.polymtl.ca/39629/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401013","display_name":"PolyPublie (\u00c9cole Polytechnique de Montr\u00e9al)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I45683168","host_organization_name":"Polytechnique Montr\u00e9al","host_organization_lineage":["https://openalex.org/I45683168"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Communication de conf\u00e9rence"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W196991832","https://openalex.org/W1977850862","https://openalex.org/W1978662529","https://openalex.org/W1995812446","https://openalex.org/W2085879890","https://openalex.org/W2090071917","https://openalex.org/W2094998159","https://openalex.org/W2095993144","https://openalex.org/W2120665166","https://openalex.org/W2124408528","https://openalex.org/W2127335869","https://openalex.org/W2137708693","https://openalex.org/W2144931012"],"related_works":["https://openalex.org/W2293118914","https://openalex.org/W2998381397","https://openalex.org/W4236419692","https://openalex.org/W3167919718","https://openalex.org/W4251718783","https://openalex.org/W2999668243","https://openalex.org/W1998888015","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"Field-Programmable-Gate-Arrays":[0],"are":[1,133,184,204],"used":[2],"increasingly":[3],"to":[4,34,81,127,167,206],"speed":[5],"up":[6],"applications":[7],"in":[8],"various":[9],"fields":[10],"of":[11,20,32,63,95,110,150,170,190],"science.":[12],"But":[13],"as":[14,98],"modern":[15],"digital":[16],"designs":[17],"integrate":[18],"hundreds":[19],"interconnected":[21],"processing":[22],"and":[23,55,73,104,136,179,192,217],"memory":[24],"units,":[25],"the":[26,60,65,108,114,139,148,168,201],"need":[27],"for":[28],"a":[29,43,92,144,180,187],"higher":[30],"level":[31,62],"abstraction":[33],"handle":[35],"their":[36],"descriptions":[37],"is":[38,165],"indisputable.":[39],"This":[40],"paper":[41],"presents":[42],"beyond-RTL":[44],"concurrent":[45],"hardware":[46],"description":[47,89,94],"language":[48],"that":[49,75,142,152,200],"combines":[50],"both":[51],"Finite-State":[52],"Machine":[53],"(FSM)":[54],"constraint":[56],"programming":[57],"paradigms.":[58],"At":[59],"featured":[61],"abstraction,":[64],"user":[66],"describes":[67],"dynamic":[68],"connections":[69],"between":[70],"data":[71,85,99,115],"sources":[72],"sinks":[74],"may":[76,125],"not":[77],"always":[78],"be":[79,154],"ready":[80],"send":[82],"or":[83,129],"receive":[84],"tokens.":[86],"The":[87,160],"high-level":[88],"methodology":[90,164],"enables":[91],"comprehensible":[93],"behaviors":[96],"such":[97],"transfer":[100],"synchronization,":[101],"exclusivity,":[102],"priority":[103],"constrained":[105],"scheduling":[106],"by":[107,138],"means":[109],"logical-implication":[111],"rules":[112],"constraining":[113],"transfers":[116,151],"authorizations.":[117],"Dynamically":[118],"connecting":[119],"resources":[120],"with":[121,186,209,213],"potential":[122],"combinatorial":[123],"dependencies":[124],"lead":[126],"instability":[128],"deadlock.":[130],"Such":[131],"situations":[132],"automatically":[134,193],"detected":[135],"fixed":[137],"proposed":[140,161],"compiler":[141],"generates":[143],"dedicated":[145],"control-circuit":[146],"optimizing":[147],"number":[149],"can":[153],"authorized":[155],"at":[156],"each":[157],"clock":[158],"cycle.":[159],"design":[162],"automation":[163],"applied":[166],"problem":[169],"deeply-pipelined":[171],"vector":[172],"reduction.":[173],"A":[174],"pipelined":[175],"floating":[176],"point":[177],"accumulator":[178],"matrix":[181],"multiplication":[182],"circuits":[183],"described":[185],"few":[188],"lines":[189],"code":[191],"compiled":[194],"into":[195],"an":[196],"FPGA.":[197],"Results":[198],"show":[199],"synthesis":[202],"results":[203],"comparable":[205],"those":[207],"obtained":[208],"hand-written":[210],"RTL":[211],"but":[212],"much":[214],"lower":[215],"effort":[216],"time.":[218]},"counts_by_year":[],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}