{"id":"https://openalex.org/W2004709743","doi":"https://doi.org/10.1145/2435264.2435333","title":"Exploiting algorithmic-level memory parallelism in distributed logic-memory architecture through hardware-assisted dynamic graph (abstract only)","display_name":"Exploiting algorithmic-level memory parallelism in distributed logic-memory architecture through hardware-assisted dynamic graph (abstract only)","publication_year":2013,"publication_date":"2013-02-11","ids":{"openalex":"https://openalex.org/W2004709743","doi":"https://doi.org/10.1145/2435264.2435333","mag":"2004709743"},"language":"en","primary_location":{"id":"doi:10.1145/2435264.2435333","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2435264.2435333","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102764809","display_name":"Yu Bai","orcid":"https://orcid.org/0000-0003-0464-1916"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Yu Bai","raw_affiliation_strings":["UCF, Orlando, FL, USA"],"affiliations":[{"raw_affiliation_string":"UCF, Orlando, FL, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029369494","display_name":"Abigail Fuentes","orcid":null},"institutions":[{"id":"https://openalex.org/I106165777","display_name":"University of Central Florida","ror":"https://ror.org/036nfer12","country_code":"US","type":"education","lineage":["https://openalex.org/I106165777"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Abigail Fuentes","raw_affiliation_strings":["University of Central Florida, Orlando, FL, USA"],"affiliations":[{"raw_affiliation_string":"University of Central Florida, Orlando, FL, USA","institution_ids":["https://openalex.org/I106165777"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060908808","display_name":"Mingjie Lin","orcid":"https://orcid.org/0000-0002-3225-4406"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mingjie Lin","raw_affiliation_strings":["UCF, Orlando, FL, USA"],"affiliations":[{"raw_affiliation_string":"UCF, Orlando, FL, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048441430","display_name":"Mike Riera","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mike Riera","raw_affiliation_strings":["UCF, Orlando, FL, USA"],"affiliations":[{"raw_affiliation_string":"UCF, Orlando, FL, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5102764809"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.07892152,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"273","last_page":"273"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8388654589653015},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6353163719177246},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5510827898979187},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5390427112579346},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.5069828033447266},{"id":"https://openalex.org/keywords/computing-with-memory","display_name":"Computing with Memory","score":0.43858957290649414},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.43077442049980164},{"id":"https://openalex.org/keywords/distributed-memory","display_name":"Distributed memory","score":0.41488635540008545},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.4042191803455353},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3648706078529358},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3301819860935211},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.29670900106430054},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.27659931778907776},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.26538175344467163}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8388654589653015},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6353163719177246},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5510827898979187},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5390427112579346},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.5069828033447266},{"id":"https://openalex.org/C152890283","wikidata":"https://www.wikidata.org/wiki/Q4129922","display_name":"Computing with Memory","level":5,"score":0.43858957290649414},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.43077442049980164},{"id":"https://openalex.org/C91481028","wikidata":"https://www.wikidata.org/wiki/Q1054686","display_name":"Distributed memory","level":3,"score":0.41488635540008545},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.4042191803455353},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3648706078529358},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3301819860935211},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.29670900106430054},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27659931778907776},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.26538175344467163},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2435264.2435333","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2435264.2435333","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3180803030","https://openalex.org/W3025845664","https://openalex.org/W2993507867","https://openalex.org/W254684032","https://openalex.org/W4293054943","https://openalex.org/W2526783553","https://openalex.org/W4312264564","https://openalex.org/W2036525499","https://openalex.org/W2143690511","https://openalex.org/W2135236335"],"abstract_inverted_index":{"Emerging":[0],"FPGA":[1,64],"device,":[2],"integrated":[3],"with":[4,138,183,203],"abundant":[5],"RAM":[6],"blocks":[7],"and":[8,35,71,77,85,189,221,225],"high-performance":[9],"processor":[10],"cores,":[11],"offers":[12],"an":[13,63,178],"unprecedented":[14],"opportunity":[15],"to":[16,62,95,196],"effectively":[17,153],"implement":[18],"single-chip":[19],"distributed":[20,192],"logic-memory":[21],"(DLM)":[22],"architectures.":[23],"Being":[24],"\"memory-centric\",":[25],"the":[26,32,111,134,165,190,229,242],"DLM":[27,57,136,174],"architecture":[28,58,137,175,218],"can":[29,144],"significantly":[30],"improve":[31],"overall":[33],"performance":[34,230],"energy":[36],"efficiency":[37],"of":[38,68,97,167,232],"many":[39],"memory-intensive":[40],"embedded":[41],"applications,":[42],"especially":[43],"those":[44],"that":[45,121,143,214],"exhibit":[46],"irregular":[47],"array":[48],"data":[49,81],"access":[50],"patterns":[51],"at":[52],"algorithmic":[53,155],"level.":[54],"However,":[55],"implementing":[56],"poses":[59],"unique":[60],"challenges":[61],"designer":[65],"in":[66],"terms":[67],"1)":[69,101],"organizing":[70],"partitioning":[72,107,119],"diverse":[73],"on-chip":[74,84],"memory":[75,106,118,124,150,157,187,245],"resources,":[76],"2)":[78,131],"orchestrating":[79],"effective":[80],"transmission":[82],"between":[83,149],"off-chip":[86],"memory.":[87],"In":[88],"this":[89],"paper,":[90],"we":[91,102,132],"offer":[92],"our":[93,168,210,215],"solutions":[94,120],"both":[96],"these":[98],"challenges.":[99],"Specifically,":[100],"propose":[103],"a":[104,139,160,184,204],"stochastic":[105],"scheme":[108],"based":[109],"on":[110,159],"well-known":[112],"simulated":[113],"annealing":[114],"algorithm.":[115],"It":[116],"obtains":[117],"promote":[122],"parallelized":[123],"accesses":[125],"by":[126,223],"exploring":[127],"large":[128],"solution":[129],"space;":[130],"augment":[133],"proposed":[135,216],"reconfigure":[140],"hardware":[141,243],"graph":[142],"dynamically":[145],"compute":[146],"precedence":[147],"relationship":[148],"partitions,":[151],"thus":[152],"exploiting":[154],"level":[156],"parallelism":[158],"per-application":[161],"basis.":[162],"We":[163],"evaluate":[164],"effectiveness":[166],"approach":[169],"(A3)":[170],"against":[171],"two":[172],"other":[173],"synthesizing":[176],"methods:":[177],"algorithmic-centric":[179],"reconfigurable":[180],"computing":[181],"architectures":[182,193],"single":[185],"monolithic":[186],"(A1)":[188],"heterogeneous":[191],"synthesized":[194],"according":[195],"(A2).":[197],"All":[198],"experiments":[199],"have":[200],"been":[201],"conducted":[202],"Virtex-5":[205],"(XCV5LX155T-2)":[206],"FPGA.":[207],"On":[208],"average,":[209],"experimental":[211],"results":[212],"show":[213],"A3":[217,233],"outperforms":[219],"A2":[220],"A1":[222],"34%":[224],"250%,":[226],"respectively.":[227],"Within":[228],"improvement":[231,239],"over":[234],"A2,":[235],"more":[236],"than":[237],"70%":[238],"comes":[240],"from":[241],"graph-based":[244],"scheduling.":[246]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
