{"id":"https://openalex.org/W1967468490","doi":"https://doi.org/10.1145/2435264.2435327","title":"A novel FPGA design framework with VLSI post-routing performance analysis (abstract only)","display_name":"A novel FPGA design framework with VLSI post-routing performance analysis (abstract only)","publication_year":2013,"publication_date":"2013-02-11","ids":{"openalex":"https://openalex.org/W1967468490","doi":"https://doi.org/10.1145/2435264.2435327","mag":"1967468490"},"language":"en","primary_location":{"id":"doi:10.1145/2435264.2435327","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2435264.2435327","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051831948","display_name":"Qian Zhao","orcid":"https://orcid.org/0000-0003-0032-1974"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Qian Zhao","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102114017","display_name":"Kazuki Inoue","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kazuki Inoue","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012465812","display_name":"Motoki Amagasaki","orcid":"https://orcid.org/0000-0002-5196-9765"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Motoki Amagasaki","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059705629","display_name":"Masahiro Iida","orcid":"https://orcid.org/0000-0002-9654-2319"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Iida","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109427367","display_name":"Morihiro Kuga","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Morihiro Kuga","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031401749","display_name":"Toshinori Sueyoshi","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Toshinori Sueyoshi","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5051831948"],"corresponding_institution_ids":["https://openalex.org/I96036126"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.04602278,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"271","last_page":"271"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9194422364234924},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8025534152984619},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7547679543495178},{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.69770747423172},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5839526057243347},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5429738163948059},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5068681836128235},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4266243577003479},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4180218577384949},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.1422792375087738},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.0774196982383728}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9194422364234924},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8025534152984619},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7547679543495178},{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.69770747423172},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5839526057243347},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5429738163948059},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5068681836128235},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4266243577003479},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4180218577384949},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.1422792375087738},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0774196982383728}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2435264.2435327","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2435264.2435327","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.44999998807907104}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1978599303","https://openalex.org/W2035847677","https://openalex.org/W2038841572","https://openalex.org/W2047143252","https://openalex.org/W2095431940","https://openalex.org/W2111756578","https://openalex.org/W2138383740","https://openalex.org/W2145897936","https://openalex.org/W2155316178","https://openalex.org/W2168493238","https://openalex.org/W2170034300","https://openalex.org/W2171549192"],"related_works":["https://openalex.org/W4319430423","https://openalex.org/W4390224957","https://openalex.org/W4323831234","https://openalex.org/W2544043553","https://openalex.org/W4311839959","https://openalex.org/W2121309702","https://openalex.org/W1982685694","https://openalex.org/W49599899","https://openalex.org/W3217774925","https://openalex.org/W2040087757"],"abstract_inverted_index":{"The":[0],"most":[1,46],"widely":[2],"used":[3,35],"open-source":[4],"field-programmable":[5],"gate":[6],"array":[7],"(FPGA)":[8],"placement":[9,22],"and":[10,23,25,28,148,172,192],"routing":[11,120],"tool":[12,121],"is":[13,82,122,130,141],"VPR,":[14,153],"which":[15,154],"can":[16,165,182],"define":[17],"the":[18,57,75,78,86,95,99,133,143,156,173,179],"target":[19],"FPGA,":[20],"perform":[21],"routing,":[24],"report":[26],"area":[27],"timing":[29],"information.":[30],"However,":[31],"it":[32,62],"cannot":[33,52],"be":[34,183],"in":[36,94,110,124],"FPGA":[37,49,92,106,113,119,180],"IP":[38,93,114,181],"design":[39,96,107,115],"efficiently":[40],"for":[41,45,60,85],"two":[42],"reasons.":[43],"First,":[44],"newly":[47],"developed":[48,123,131],"architectures,":[50],"VPR":[51,59,79],"support":[53],"them":[54],"directly.":[55],"Modifying":[56],"C-coded":[58],"using":[61,132,160],"to":[63,152],"evaluate":[64],"a":[65,71,89,105],"number":[66],"of":[67,77,88,101],"new":[68],"architectures":[69],"requires":[70],"long":[72],"time.":[73,158],"Second,":[74],"accuracy":[76,191],"performance":[80],"results":[81],"not":[83],"enough":[84],"evaluation":[87],"complete":[90],"synthesizable":[91],"that":[97,109],"targets":[98],"productions":[100],"LSI.":[102],"We":[103],"propose":[104],"framework":[108],"particular":[111],"improves":[112],"efficiency.":[116],"A":[117],"novel":[118],"this":[125],"framework,":[126],"namely":[127],"EasyRouter.":[128],"EasyRouter":[129,164],"C#":[134],"language.":[135],"When":[136],"an":[137],"object-oriented":[138],"programming":[139],"method":[140],"used,":[142],"source":[144],"codes":[145,171],"are":[146],"fewer":[147],"easier":[149],"manage":[150],"compared":[151],"shortens":[155],"development":[157],"By":[159],"simple":[161],"HDL":[162,170],"templates,":[163],"automatically":[166],"generate":[167],"entire":[168],"chip":[169],"configuration":[174],"bitstream.":[175],"With":[176],"these":[177],"files,":[178],"evaluated":[184],"with":[185,189],"commercial":[186],"VLSI":[187],"CADs":[188],"high":[190],"reliability.":[193]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}