{"id":"https://openalex.org/W2041094836","doi":"https://doi.org/10.1145/2435264.2435324","title":"Achieving modular dynamic partial reconfiguration with a difference-based flow (abstract only)","display_name":"Achieving modular dynamic partial reconfiguration with a difference-based flow (abstract only)","publication_year":2013,"publication_date":"2013-02-11","ids":{"openalex":"https://openalex.org/W2041094836","doi":"https://doi.org/10.1145/2435264.2435324","mag":"2041094836"},"language":"en","primary_location":{"id":"doi:10.1145/2435264.2435324","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2435264.2435324","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069036699","display_name":"Sezer G\u00f6ren","orcid":"https://orcid.org/0000-0002-3688-5280"},"institutions":[{"id":"https://openalex.org/I100072489","display_name":"Yeditepe University","ror":"https://ror.org/025mx2575","country_code":"TR","type":"education","lineage":["https://openalex.org/I100072489"]}],"countries":["TR"],"is_corresponding":true,"raw_author_name":"Sezer G\u00f6ren","raw_affiliation_strings":["Yeditepe University, Istanbul, Turkey","Yeditepe University , Istanbul , Turkey"],"affiliations":[{"raw_affiliation_string":"Yeditepe University, Istanbul, Turkey","institution_ids":["https://openalex.org/I100072489"]},{"raw_affiliation_string":"Yeditepe University , Istanbul , Turkey","institution_ids":["https://openalex.org/I100072489"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090442511","display_name":"Yusuf Turk","orcid":null},"institutions":[{"id":"https://openalex.org/I100072489","display_name":"Yeditepe University","ror":"https://ror.org/025mx2575","country_code":"TR","type":"education","lineage":["https://openalex.org/I100072489"]}],"countries":["TR"],"is_corresponding":false,"raw_author_name":"Yusuf Turk","raw_affiliation_strings":["Yeditepe University, Istanbul, Turkey","Yeditepe University , Istanbul , Turkey"],"affiliations":[{"raw_affiliation_string":"Yeditepe University, Istanbul, Turkey","institution_ids":["https://openalex.org/I100072489"]},{"raw_affiliation_string":"Yeditepe University , Istanbul , Turkey","institution_ids":["https://openalex.org/I100072489"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065512264","display_name":"Ozgur Ozkurt","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ozgur Ozkurt","raw_affiliation_strings":["Vestek R&amp;D, Istanbul, Turkey"],"affiliations":[{"raw_affiliation_string":"Vestek R&amp;D, Istanbul, Turkey","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033557753","display_name":"Abdullah Y\u0131ld\u0131z","orcid":"https://orcid.org/0000-0001-9752-9370"},"institutions":[{"id":"https://openalex.org/I100072489","display_name":"Yeditepe University","ror":"https://ror.org/025mx2575","country_code":"TR","type":"education","lineage":["https://openalex.org/I100072489"]}],"countries":["TR"],"is_corresponding":false,"raw_author_name":"Abdullah Yildiz","raw_affiliation_strings":["Yeditepe University, Istanbul, Turkey","Yeditepe University , Istanbul , Turkey"],"affiliations":[{"raw_affiliation_string":"Yeditepe University, Istanbul, Turkey","institution_ids":["https://openalex.org/I100072489"]},{"raw_affiliation_string":"Yeditepe University , Istanbul , Turkey","institution_ids":["https://openalex.org/I100072489"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029193455","display_name":"H. Fatih U\u011furda\u011f","orcid":"https://orcid.org/0000-0002-6256-0850"},"institutions":[{"id":"https://openalex.org/I44925452","display_name":"\u00d6zye\u011fin University","ror":"https://ror.org/01jjhfr75","country_code":"TR","type":"education","lineage":["https://openalex.org/I44925452"]}],"countries":["TR"],"is_corresponding":false,"raw_author_name":"H. Fatih Ugurdag","raw_affiliation_strings":["Ozyegin University, Istanbul, Turkey"],"affiliations":[{"raw_affiliation_string":"Ozyegin University, Istanbul, Turkey","institution_ids":["https://openalex.org/I44925452"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5069036699"],"corresponding_institution_ids":["https://openalex.org/I100072489"],"apc_list":null,"apc_paid":null,"fwci":1.2608,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.80091063,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"270","last_page":"270"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8162251710891724},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.7817853689193726},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7284135818481445},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5849946737289429},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5320656895637512},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5139958262443542},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4960952699184418},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.4411761462688446},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3340308666229248},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.16748085618019104},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07584625482559204}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8162251710891724},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.7817853689193726},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7284135818481445},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5849946737289429},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5320656895637512},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5139958262443542},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4960952699184418},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.4411761462688446},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3340308666229248},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16748085618019104},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07584625482559204},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2435264.2435324","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2435264.2435324","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4399999976158142,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2020424968","https://openalex.org/W2080061332","https://openalex.org/W2091911576","https://openalex.org/W2114494919"],"related_works":["https://openalex.org/W2808484818","https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W2340647897","https://openalex.org/W4249632163","https://openalex.org/W1760305469","https://openalex.org/W2797161794","https://openalex.org/W2073075351","https://openalex.org/W2096938998"],"abstract_inverted_index":{"Dynamic":[0],"Partial":[1],"Reconfiguration":[2],"(DPR)":[3],"of":[4,60,122,156],"Xilinx":[5,22,26,40,64,82],"FPGAs":[6,33,65],"in":[7,187],"cases":[8],"where":[9],"there":[10],"is":[11,18,91],"significant":[12],"logic":[13],"difference":[14],"between":[15,97],"subsequent":[16,98],"configurations":[17],"made":[19],"possible":[20],"by":[21],"module-based":[23],"PR":[24],"flow.":[25,243],"supports":[27],"this":[28],"flow":[29,113],"only":[30,93],"for":[31,73,75,94,145],"high-end":[32,63],"and":[34,47,62,66,124,131,149,199,208],"requires":[35,67,114],"paid":[36,69],"license,":[37],"without":[38,209],"which":[39,89],"PlanAhead":[41,189,242],"software":[42,87],"disables":[43],"the":[44,80,136,170,184,191,200,215],"related":[45],"knobs":[46],"features.":[48],"This":[49],"poster":[50],"presents":[51],"a":[52,157,197,218,222,233],"unique":[53],"methodology":[54],"(called":[55],"DPR-LD)":[56],"that":[57],"enables":[58],"DPR":[59,74],"low-end":[61],"no":[68],"license.":[70],"DPR-LD":[71,78,100],"stands":[72],"Large":[76],"Differences.":[77],"uses":[79],"free":[81],"difference-based":[83],"bit":[84],"file":[85],"generation":[86],"(bitgen),":[88],"normally":[90],"meant":[92],"small":[95],"differences":[96],"configurations.":[99],"can":[101],"be":[102],"realized":[103],"through":[104],"either":[105],"FPGA":[106,111,181,211],"Editor":[107,112],"or":[108],"PlanAhead.":[109],"Our":[110],"several":[115,139],"physical":[116,140,192,203],"constraints":[117,133,193,204],"to":[118,134,153,159,168,179],"ensure":[119],"contention-free":[120],"implementation":[121],"static":[123],"dynamic":[125,224,235],"modules.":[126],"We":[127],"use":[128],"implementation,":[129],"floorplanning,":[130],"placement":[132],"partition":[135],"design":[137,237],"into":[138],"regions":[141],"(one":[142],"per":[143],"module)":[144],"mapping,":[146],"packing,":[147],"placement,":[148],"routing.":[150],"In":[151,231],"order":[152],"avoid":[154],"routing":[155],"module":[158],"cross":[160],"over":[161],"another":[162],"module,":[163],"\"fortress":[164],"block\"s":[165],"are":[166,194,205],"used":[167],"isolate":[169],"modules":[171],"from":[172],"each":[173],"other.":[174],"However,":[175],"fortress":[176],"blocks":[177],"lead":[178],"wasted":[180],"resources.":[182,212],"On":[183],"other":[185],"hand,":[186],"our":[188,241],"flow,":[190],"entered":[195],"via":[196],"GUI,":[198],"corresponding":[201],"actual":[202],"generated":[206],"automatically":[207],"wasting":[210],"To":[213],"evaluate":[214],"two":[216],"approaches,":[217],"proof-of-concept":[219],"application":[220],"with":[221,240],"single":[223],"region":[225,236],"was":[226,238],"implemented":[227,239],"using":[228],"both":[229],"flows.":[230],"addition,":[232],"multiple":[234]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
