{"id":"https://openalex.org/W2038478630","doi":"https://doi.org/10.1145/2435264.2435302","title":"C-to-CoRAM","display_name":"C-to-CoRAM","publication_year":2013,"publication_date":"2013-02-11","ids":{"openalex":"https://openalex.org/W2038478630","doi":"https://doi.org/10.1145/2435264.2435302","mag":"2038478630"},"language":"en","primary_location":{"id":"doi:10.1145/2435264.2435302","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2435264.2435302","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082282602","display_name":"Gabriel Weisz","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Gabriel Weisz","raw_affiliation_strings":["Carnegie Mellon University, Pittsburgh, PA, USA","Carnegie-Mellon University, Pittsburgh, Pa., USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Carnegie-Mellon University, Pittsburgh, Pa., USA#TAB#","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5019376179","display_name":"James C. Hoe","orcid":"https://orcid.org/0000-0002-9302-5287"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James C. Hoe","raw_affiliation_strings":["Carnegie Mellon University, Pittsburgh, PA, USA","Carnegie-Mellon University, Pittsburgh, Pa., USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Carnegie-Mellon University, Pittsburgh, Pa., USA#TAB#","institution_ids":["https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5082282602"],"corresponding_institution_ids":["https://openalex.org/I74973139"],"apc_list":null,"apc_paid":null,"fwci":0.9515,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.75966589,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"221","last_page":"230"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8680387735366821},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.8382463455200195},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5741991400718689},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5157747268676758},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.44447457790374756},{"id":"https://openalex.org/keywords/nested-loop-join","display_name":"Nested loop join","score":0.421242356300354},{"id":"https://openalex.org/keywords/interprocedural-optimization","display_name":"Interprocedural optimization","score":0.4180436432361603},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.33448413014411926},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.314754843711853},{"id":"https://openalex.org/keywords/compiler-correctness","display_name":"Compiler correctness","score":0.30134862661361694},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2611948847770691},{"id":"https://openalex.org/keywords/loop-optimization","display_name":"Loop optimization","score":0.16201546788215637}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8680387735366821},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.8382463455200195},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5741991400718689},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5157747268676758},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.44447457790374756},{"id":"https://openalex.org/C1306188","wikidata":"https://www.wikidata.org/wiki/Q4060687","display_name":"Nested loop join","level":2,"score":0.421242356300354},{"id":"https://openalex.org/C111564260","wikidata":"https://www.wikidata.org/wiki/Q4288856","display_name":"Interprocedural optimization","level":5,"score":0.4180436432361603},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.33448413014411926},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.314754843711853},{"id":"https://openalex.org/C68366613","wikidata":"https://www.wikidata.org/wiki/Q5156378","display_name":"Compiler correctness","level":3,"score":0.30134862661361694},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2611948847770691},{"id":"https://openalex.org/C29331672","wikidata":"https://www.wikidata.org/wiki/Q3354468","display_name":"Loop optimization","level":4,"score":0.16201546788215637}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2435264.2435302","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2435264.2435302","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1515448847","https://openalex.org/W1976878754","https://openalex.org/W1979081194","https://openalex.org/W1990525787","https://openalex.org/W1995441293","https://openalex.org/W2018055497","https://openalex.org/W2020458826","https://openalex.org/W2022128349","https://openalex.org/W2034761517","https://openalex.org/W2046607278","https://openalex.org/W2058733701","https://openalex.org/W2091990457","https://openalex.org/W2098420952","https://openalex.org/W2105853930","https://openalex.org/W2112678088","https://openalex.org/W2113755305","https://openalex.org/W2115704989","https://openalex.org/W2151034090","https://openalex.org/W2154991996","https://openalex.org/W2606963276","https://openalex.org/W3203568064"],"related_works":["https://openalex.org/W2094199724","https://openalex.org/W4246454774","https://openalex.org/W2121223013","https://openalex.org/W2169584677","https://openalex.org/W4232954277","https://openalex.org/W3000589862","https://openalex.org/W2749133591","https://openalex.org/W2354057234","https://openalex.org/W3007855180","https://openalex.org/W4240253816"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"initial":[3],"work":[4],"on":[5,20,28,119,156,185,212],"developing":[6],"a":[7,70,113,126,195,201],"C":[8],"compiler":[9,42,88,142,168],"for":[10],"the":[11,38,41,59,73,81,107,133,157,161,173,186,188],"CoRAM":[12,39,108,123],"FPGA":[13,103,115],"computing":[14],"abstraction.":[15],"The":[16,87,122,141],"presented":[17],"effort":[18],"focuses":[19],"compiling":[21],"fixed-bound":[22],"perfect":[23],"loop":[24],"nests":[25],"that":[26,67,105,166],"operate":[27],"large":[29],"data":[30,78],"sets":[31],"in":[32,69,112,117],"external":[33,85],"DRAM.":[34,86],"As":[35],"required":[36],"by":[37],"abstraction,":[40,109],"partitions":[43],"source":[44],"code":[45],"into":[46],"two":[47],"separate":[48],"implementation":[49],"components:":[50],"(1)":[51],"hardware":[52,82],"kernel":[53],"pipelines":[54],"to":[55,91,131,171,200,207],"be":[56],"mapped":[57],"onto":[58],"reconfigurable":[60],"logic":[61],"fabric;":[62],"and":[63,75,84,94,138,153,160,176,182],"(2)":[64],"control":[65],"threads":[66],"express,":[68],"C-like":[71],"language,":[72],"sequencing":[74],"coordination":[76],"of":[77,135,197,203],"transfers":[79],"between":[80],"kernels":[83],"performs":[89],"optimizations":[90],"increase":[92],"parallelism":[93],"use":[95],"DRAM":[96],"bandwidth":[97],"efficiently.":[98],"It":[99],"can":[100],"target":[101,130,172],"different":[102,174],"platforms":[104,175],"support":[106],"either":[110],"natively":[111],"future":[114],"or":[116],"soft-logic":[118],"today's":[120],"devices.":[121],"abstraction":[124],"provides":[125],"convenient":[127],"high-level":[128],"compilation":[129],"simplify":[132],"task":[134],"design":[136],"optimization":[137],"system":[139],"generation.":[140],"is":[143,169],"evaluated":[144],"using":[145],"three":[146],"test":[147],"programs":[148],"(matrix-matrix":[149],"multiplication,":[150],"k-nearest":[151],"neighbor,":[152],"2D":[154],"convolution)":[155],"Xilinx":[158],"ML605":[159],"Altera":[162],"DE4.":[163],"Results":[164],"show":[165],"our":[167],"able":[170],"effectively":[177],"exploit":[178],"their":[179],"dissimilar":[180],"capacities":[181],"features.":[183],"Depending":[184],"application,":[187],"compiler-generated":[189],"implementations":[190],"achieve":[191],"performance":[192],"ranging":[193],"from":[194],"factor":[196,202],"4":[198],"slower":[199],"2":[204],"faster":[205],"relative":[206],"hand-designed":[208],"implementations,":[209],"as":[210],"measured":[211],"actual":[213],"hardware.":[214]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2026-04-28T14:05:53.105641","created_date":"2016-06-24T00:00:00"}