{"id":"https://openalex.org/W2043526161","doi":"https://doi.org/10.1145/2435264.2435301","title":"A remote memory access infrastructure for global address space programming models in FPGAs","display_name":"A remote memory access infrastructure for global address space programming models in FPGAs","publication_year":2013,"publication_date":"2013-02-11","ids":{"openalex":"https://openalex.org/W2043526161","doi":"https://doi.org/10.1145/2435264.2435301","mag":"2043526161"},"language":"en","primary_location":{"id":"doi:10.1145/2435264.2435301","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2435264.2435301","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002287804","display_name":"Ruediger Willenberg","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Ruediger Willenberg","raw_affiliation_strings":["University of Toronto, Toronto, ON, Canada","University of Toronto, Toronto, On, Canada"],"affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"University of Toronto, Toronto, On, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035437657","display_name":"Paul Chow","orcid":"https://orcid.org/0000-0002-0523-7117"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Paul Chow","raw_affiliation_strings":["University of Toronto, Toronto, ON, Canada","University of Toronto, Toronto, On, Canada"],"affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"University of Toronto, Toronto, On, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5002287804"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":1.8913,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.85822694,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"211","last_page":"220"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8176679015159607},{"id":"https://openalex.org/keywords/partitioned-global-address-space","display_name":"Partitioned global address space","score":0.7853796482086182},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7046837210655212},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5150496959686279},{"id":"https://openalex.org/keywords/programming-paradigm","display_name":"Programming paradigm","score":0.5098516345024109},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4890928864479065},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4794405996799469},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.45015308260917664},{"id":"https://openalex.org/keywords/distributed-memory","display_name":"Distributed memory","score":0.43992123007774353},{"id":"https://openalex.org/keywords/address-space","display_name":"Address space","score":0.43862012028694153},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43295568227767944},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.4169413149356842},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.32287806272506714},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2866777777671814},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.13307246565818787},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.08797207474708557}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8176679015159607},{"id":"https://openalex.org/C60832428","wikidata":"https://www.wikidata.org/wiki/Q945818","display_name":"Partitioned global address space","level":3,"score":0.7853796482086182},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7046837210655212},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5150496959686279},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.5098516345024109},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4890928864479065},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4794405996799469},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.45015308260917664},{"id":"https://openalex.org/C91481028","wikidata":"https://www.wikidata.org/wiki/Q1054686","display_name":"Distributed memory","level":3,"score":0.43992123007774353},{"id":"https://openalex.org/C144240696","wikidata":"https://www.wikidata.org/wiki/Q367204","display_name":"Address space","level":2,"score":0.43862012028694153},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43295568227767944},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.4169413149356842},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32287806272506714},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2866777777671814},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13307246565818787},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.08797207474708557},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2435264.2435301","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2435264.2435301","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6200000047683716,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W13759931","https://openalex.org/W1982516565","https://openalex.org/W2003856929","https://openalex.org/W2019957762","https://openalex.org/W2069079195","https://openalex.org/W2109065830","https://openalex.org/W2112678088","https://openalex.org/W2112726960","https://openalex.org/W2149970695","https://openalex.org/W2155066383","https://openalex.org/W2155384680","https://openalex.org/W2169816952","https://openalex.org/W4401102712"],"related_works":["https://openalex.org/W1945291735","https://openalex.org/W3172565186","https://openalex.org/W2116089877","https://openalex.org/W2138782497","https://openalex.org/W1559683866","https://openalex.org/W2182797201","https://openalex.org/W1935251877","https://openalex.org/W990235011","https://openalex.org/W2921618608","https://openalex.org/W4232195385"],"abstract_inverted_index":{"We":[0,81],"are":[1],"proposing":[2],"a":[3,9,20,48,69,87,98],"shared-memory":[4],"communication":[5,66,74,92],"infrastructure":[6],"that":[7,57,72],"provides":[8],"common":[10],"parallel":[11,34],"programming":[12,35],"interface":[13],"for":[14,77],"FPGA":[15,79],"and":[16,68,75,89],"CPU":[17],"components":[18,85],"in":[19,97],"heterogeneous":[21],"system.":[22],"Our":[23],"intent":[24],"is":[25],"to":[26],"ease":[27],"the":[28,59,63],"integration":[29],"of":[30,62],"reconfigurable":[31],"hardware":[32,107],"into":[33],"models":[36],"like":[37],"Partitioned":[38],"Global":[39],"Address":[40],"Space":[41],"(PGAS).":[42],"For":[43],"this":[44],"purpose,":[45],"we":[46],"introduce":[47],"remote":[49],"memory":[50],"access":[51],"component":[52],"based":[53],"on":[54],"Active":[55],"Messages":[56],"implements":[58],"core":[60],"API":[61],"Berkeley":[64],"GASNet":[65],"library,":[67],"simple":[70,88],"controller":[71],"manages":[73],"synchronization":[76],"custom":[78,106],"cores.":[80],"demonstrate":[82],"how":[83],"these":[84],"deliver":[86],"easily":[90],"configurable":[91],"mechanism":[93],"between":[94],"distributed":[95],"memories":[96],"multi-FPGA":[99],"system":[100],"with":[101],"processors":[102],"as":[103,105],"well":[104],"nodes.":[108]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}