{"id":"https://openalex.org/W2023146792","doi":"https://doi.org/10.1145/2435264.2435292","title":"Architectural enhancements in Stratix V\u2122","display_name":"Architectural enhancements in Stratix V\u2122","publication_year":2013,"publication_date":"2013-02-11","ids":{"openalex":"https://openalex.org/W2023146792","doi":"https://doi.org/10.1145/2435264.2435292","mag":"2023146792"},"language":"en","primary_location":{"id":"doi:10.1145/2435264.2435292","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2435264.2435292","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102968798","display_name":"David Lewis","orcid":"https://orcid.org/0000-0002-8126-5662"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"David Lewis","raw_affiliation_strings":["Altera, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Altera, Toronto, ON, Canada","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002057044","display_name":"David Cashman","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"David Cashman","raw_affiliation_strings":["Altera, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Altera, Toronto, ON, Canada","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070704694","display_name":"Mark Chan","orcid":null},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark Chan","raw_affiliation_strings":["Altera, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Altera, San Jose, CA, USA","institution_ids":["https://openalex.org/I22433950"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030209953","display_name":"Jeffery Chromczak","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jeffery Chromczak","raw_affiliation_strings":["Altera, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Altera, Toronto, ON, Canada","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022181201","display_name":"Gary Lai","orcid":null},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gary Lai","raw_affiliation_strings":["Altera, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Altera, San Jose, CA, USA","institution_ids":["https://openalex.org/I22433950"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006498333","display_name":"Andy Lee","orcid":"https://orcid.org/0000-0002-8546-5311"},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andy Lee","raw_affiliation_strings":["Altera, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Altera, San Jose, CA, USA","institution_ids":["https://openalex.org/I22433950"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035149504","display_name":"Tim Vanderhoek","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tim Vanderhoek","raw_affiliation_strings":["Altera, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Altera, Toronto, ON, Canada","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014685695","display_name":"Haiming Yu","orcid":"https://orcid.org/0000-0002-3291-6713"},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Haiming Yu","raw_affiliation_strings":["Altera, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Altera, San Jose, CA, USA","institution_ids":["https://openalex.org/I22433950"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5102968798"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":5.0492,"has_fulltext":false,"cited_by_count":65,"citation_normalized_percentile":{"value":0.95605881,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"147","last_page":"156"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.9121668338775635},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.7831056118011475},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6827703714370728},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6796969175338745},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6453652381896973},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5537704229354858},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5457422733306885},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5423077940940857},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5413603186607361},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.4488782584667206},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.4426586329936981},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.43834584951400757},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.43451449275016785},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.42544203996658325},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41193607449531555},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4093600809574127},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4030589759349823},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3646343946456909},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22823932766914368},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08885279297828674},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.07955732941627502}],"concepts":[{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.9121668338775635},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.7831056118011475},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6827703714370728},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6796969175338745},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6453652381896973},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5537704229354858},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5457422733306885},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5423077940940857},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5413603186607361},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.4488782584667206},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.4426586329936981},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.43834584951400757},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.43451449275016785},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.42544203996658325},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41193607449531555},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4093600809574127},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4030589759349823},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3646343946456909},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22823932766914368},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08885279297828674},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.07955732941627502},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2435264.2435292","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2435264.2435292","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","score":0.47999998927116394,"display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1488567546","https://openalex.org/W1523051745","https://openalex.org/W1979432606","https://openalex.org/W2008694370","https://openalex.org/W2021708499","https://openalex.org/W2022532823","https://openalex.org/W2025474944","https://openalex.org/W2038318386","https://openalex.org/W2049960281","https://openalex.org/W2068316116","https://openalex.org/W2096568519","https://openalex.org/W2096805904","https://openalex.org/W2097950173","https://openalex.org/W2114835190","https://openalex.org/W2116094656","https://openalex.org/W2118482092","https://openalex.org/W2118637853","https://openalex.org/W2124241199","https://openalex.org/W2144786659","https://openalex.org/W2176367099"],"related_works":["https://openalex.org/W2117931353","https://openalex.org/W4230078917","https://openalex.org/W2089341644","https://openalex.org/W2023146792","https://openalex.org/W3212959636","https://openalex.org/W1490954251","https://openalex.org/W2037710643","https://openalex.org/W2126255765","https://openalex.org/W2993587745","https://openalex.org/W218334444"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"architectural":[3],"enhancements":[4],"in":[5,111],"the":[6,19,25,35,83,91,106,121,125],"Altera":[7],"Stratix-V\"":[8],"FPGA":[9],"architecture,":[10],"built":[11],"on":[12,105],"a":[13,32,46,70,98],"28nm":[14,92],"TSMC":[15],"process,":[16],"together":[17],"with":[18,73],"data":[20],"supporting":[21],"those":[22],"choices.":[23],"Among":[24],"key":[26],"features":[27],"are":[28,115],"time":[29],"borrowing":[30],"flip-flops,":[31],"doubling":[33],"of":[34,37,76,97,101,124],"number":[36],"flip-flops":[38],"per":[39],"LUT":[40],"compared":[41],"to":[42,60,94,120],"previous":[43],"Stratix":[44],"architectures,":[45],"simplified":[47],"embedded":[48],"20kb":[49],"dual-port":[50],"RAM":[51],"block,":[52],"and":[53,86,109,113],"error":[54],"correction":[55],"that":[56],"can":[57],"correct":[58],"up":[59],"8":[61],"adjacent":[62],"errors.":[63],"Arithmetic":[64],"performance":[65,112],"is":[66,88],"significantly":[67],"improved":[68],"using":[69],"fast":[71],"adder":[72],"two":[74],"levels":[75],"multi-bit":[77],"skip.":[78],"We":[79],"also":[80],"describe":[81],"how":[82],"routing":[84,128],"architecture":[85],"layout":[87],"optimized":[89],"for":[90],"process":[93],"take":[95],"advantage":[96],"wider":[99],"range":[100],"wire":[102],"thicknesses":[103],"offered":[104],"different":[107],"layers,":[108],"improvements":[110],"routability":[114],"obtained":[116],"without":[117],"dramatic":[118],"changes":[119],"repeated":[122],"floorplan":[123],"logic":[126],"plus":[127],"fabric.":[129]},"counts_by_year":[{"year":2025,"cited_by_count":8},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":8},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":6},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":7},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":10},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":1}],"updated_date":"2026-03-28T08:17:26.163206","created_date":"2025-10-10T00:00:00"}
