{"id":"https://openalex.org/W2000188956","doi":"https://doi.org/10.1145/2435264.2435266","title":"Building zynq\u00ae accelerators with Vivado\u00ae high level synthesis","display_name":"Building zynq\u00ae accelerators with Vivado\u00ae high level synthesis","publication_year":2013,"publication_date":"2013-02-11","ids":{"openalex":"https://openalex.org/W2000188956","doi":"https://doi.org/10.1145/2435264.2435266","mag":"2000188956"},"language":"en","primary_location":{"id":"doi:10.1145/2435264.2435266","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2435264.2435266","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014827775","display_name":"Stephen Neuendorffer","orcid":"https://orcid.org/0000-0003-2956-8428"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Stephen Neuendorffer","raw_affiliation_strings":["Xilinx Inc., San Jose, CA, USA","Xilinx Inc, San Jose, CA, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Xilinx Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]},{"raw_affiliation_string":"Xilinx Inc, San Jose, CA, USA#TAB#","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011268157","display_name":"Fernando Martinez-Vallina","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fernando Martinez-Vallina","raw_affiliation_strings":["Xilinx Inc., San Jose, CA, USA","Xilinx Inc, San Jose, CA, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Xilinx Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]},{"raw_affiliation_string":"Xilinx Inc, San Jose, CA, USA#TAB#","institution_ids":["https://openalex.org/I32923980"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5014827775"],"corresponding_institution_ids":["https://openalex.org/I32923980"],"apc_list":null,"apc_paid":null,"fwci":3.4673,"has_fulltext":false,"cited_by_count":25,"citation_normalized_percentile":{"value":0.9233997,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9896000027656555,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9891999959945679,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8148113489151001},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7572325468063354},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.74229896068573},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6929585933685303},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.6862412691116333},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6580948233604431},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.6322453618049622},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5809518694877625},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5047112703323364},{"id":"https://openalex.org/keywords/simple-programmable-logic-device","display_name":"Simple programmable logic device","score":0.4591924250125885},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.45249268412590027},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.41530871391296387},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2875491678714752},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.15426886081695557}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8148113489151001},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7572325468063354},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.74229896068573},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6929585933685303},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.6862412691116333},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6580948233604431},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.6322453618049622},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5809518694877625},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5047112703323364},{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.4591924250125885},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.45249268412590027},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.41530871391296387},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2875491678714752},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.15426886081695557},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2435264.2435266","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2435264.2435266","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3117015220","https://openalex.org/W1528933814","https://openalex.org/W3013792460","https://openalex.org/W1904803855","https://openalex.org/W3022525969","https://openalex.org/W2519750906","https://openalex.org/W2466591189","https://openalex.org/W4389045693","https://openalex.org/W2376859467","https://openalex.org/W2014165129"],"abstract_inverted_index":{"Engineering":[0],"complex":[1],"systems":[2],"inevitably":[3],"requires":[4],"a":[5,77],"designer":[6],"to":[7,26,80,105],"balance":[8,27],"many":[9,21],"conflicting":[10],"design":[11,18,29],"requirements":[12,30],"including":[13],"performance,":[14],"cost,":[15],"power,":[16],"and":[17,62,97,111,124],"time.":[19],"In":[20,72],"cases,":[22],"FPGAs":[23],"enable":[24],"engineers":[25],"these":[28,130],"in":[31,94],"ways":[32],"not":[33],"possible":[34],"with":[35,67],"other":[36],"technologies":[37],"like":[38],"ASICs,":[39],"ASSPs,":[40],"GPUs":[41],"or":[42],"general":[43],"purpose":[44],"processors.":[45,71],"This":[46],"tutorial":[47],"will":[48,75,100],"focus":[49],"on":[50],"two":[51],"of":[52,86,108,129],"the":[53,106,125],"newest":[54],"commercial":[55],"FPGA-related":[56],"technologies,":[57],"High":[58,121],"Level":[59,122],"Synthesis":[60,123],"(HLS)":[61],"Programmable":[63],"Logic":[64],"integrated":[65],"tightly":[66],"high":[68],"performance":[69],"embedded":[70],"particular,":[73],"we":[74],"present":[76,102],"detailed":[78],"introduction":[79,104],"Vivado":[81],"HLS,":[82],"which":[83],"is":[84],"capable":[85],"synthesizing":[87],"optimized":[88],"FPGA":[89],"circuits":[90],"from":[91],"algorithmic":[92],"descriptions":[93],"C,":[95],"C++":[96],"SystemC.":[98],"We":[99],"also":[101],"an":[103],"architecture":[107],"Zynq":[109],"devices":[110],"show":[112],"how":[113],"interesting":[114],"system":[115],"architectures":[116],"can":[117],"be":[118],"constructed":[119],"using":[120],"programmable":[126],"logic":[127],"portion":[128],"devices.":[131]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":6}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}