{"id":"https://openalex.org/W1977285867","doi":"https://doi.org/10.1145/2429384.2429437","title":"Scaling the \"memory wall\"","display_name":"Scaling the \"memory wall\"","publication_year":2012,"publication_date":"2012-11-05","ids":{"openalex":"https://openalex.org/W1977285867","doi":"https://doi.org/10.1145/2429384.2429437","mag":"1977285867"},"language":"en","primary_location":{"id":"doi:10.1145/2429384.2429437","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2429384.2429437","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Computer-Aided Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113824454","display_name":"Shih\u2010Lien Lu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shih-Lien Lu","raw_affiliation_strings":["Intel Corporation, Hillsboro Oregon","[Intel Corporation, Hillsboro, Oregon]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro Oregon","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel Corporation, Hillsboro, Oregon]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016416631","display_name":"Tanay Karnik","orcid":"https://orcid.org/0000-0003-0072-1492"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tanay Karnik","raw_affiliation_strings":["Intel Corporation, Hillsboro Oregon","[Intel Corporation, Hillsboro, Oregon]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro Oregon","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel Corporation, Hillsboro, Oregon]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053814182","display_name":"Ganapati Srinivasa","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ganapati Srinivasa","raw_affiliation_strings":["Intel Corporation, Hillsboro Oregon","[Intel Corporation, Hillsboro, Oregon]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro Oregon","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel Corporation, Hillsboro, Oregon]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061862022","display_name":"Kai-Yuan Chao","orcid":"https://orcid.org/0009-0006-1057-1319"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kai-Yuan Chao","raw_affiliation_strings":["Intel Corporation, Hillsboro Oregon","[Intel Corporation, Hillsboro, Oregon]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro Oregon","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel Corporation, Hillsboro, Oregon]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086562058","display_name":"Doug Carmean","orcid":"https://orcid.org/0009-0001-8189-3917"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Doug Carmean","raw_affiliation_strings":["Intel Corporation, Hillsboro Oregon","[Intel Corporation, Hillsboro, Oregon]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro Oregon","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel Corporation, Hillsboro, Oregon]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033480905","display_name":"Jim Held","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jim Held","raw_affiliation_strings":["Intel Corporation, Hillsboro Oregon","[Intel Corporation, Hillsboro, Oregon]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro Oregon","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel Corporation, Hillsboro, Oregon]","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.1716,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.77131748,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"271","last_page":"272"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.9318070411682129},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.7421861886978149},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6702869534492493},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5466875433921814},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.47881370782852173},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4725760221481323},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.43624699115753174},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.43391212821006775},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.433333158493042},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.42716872692108154},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.41877883672714233},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.40649840235710144},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38754796981811523},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.3709149956703186},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.33663296699523926},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2836441695690155}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.9318070411682129},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.7421861886978149},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6702869534492493},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5466875433921814},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.47881370782852173},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4725760221481323},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.43624699115753174},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.43391212821006775},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.433333158493042},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.42716872692108154},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.41877883672714233},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.40649840235710144},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38754796981811523},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.3709149956703186},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.33663296699523926},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2836441695690155},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2429384.2429437","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2429384.2429437","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Computer-Aided Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2100799944","https://openalex.org/W2151917022","https://openalex.org/W2474451066"],"related_works":["https://openalex.org/W3008068282","https://openalex.org/W2132401245","https://openalex.org/W3089341786","https://openalex.org/W2555826082","https://openalex.org/W1603816627","https://openalex.org/W2557931434","https://openalex.org/W3146736181","https://openalex.org/W2809388636","https://openalex.org/W4233769243","https://openalex.org/W2119092821"],"abstract_inverted_index":{"DRAM":[0,15,30,69],"has":[1,46],"been":[2],"the":[3,12,59,66],"technology":[4,21],"for":[5,25,74],"computer":[6],"main":[7],"memory":[8,26,37],"since":[9],"Intel":[10],"released":[11],"first":[13],"commercial":[14],"chip":[16],"(i1103)":[17],"in":[18],"1970.":[19],"As":[20],"scales":[22],"and":[23],"demand":[24],"performance,":[27],"it":[28,43,62],"seems":[29],"is":[31],"facing":[32],"several":[33],"challenges.":[34],"Many":[35],"other":[36],"technologies":[38],"are":[39],"anticipated":[40],"to":[41,64,70],"replace":[42],"but":[44],"none":[45],"emerged":[47],"as":[48],"a":[49],"clear":[50],"winner":[51],"thus":[52],"far.":[53],"In":[54],"this":[55],"paper":[56],"we":[57],"post":[58],"question.":[60],"Is":[61],"possible":[63],"re-examine":[65],"design":[67],"of":[68],"continue":[71],"its":[72],"life":[73],"another":[75],"decade":[76],"at":[77],"least?":[78]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}