{"id":"https://openalex.org/W1966131844","doi":"https://doi.org/10.1145/2382564.2382565","title":"Digital Hardware Design Teaching","display_name":"Digital Hardware Design Teaching","publication_year":2012,"publication_date":"2012-11-01","ids":{"openalex":"https://openalex.org/W1966131844","doi":"https://doi.org/10.1145/2382564.2382565","mag":"1966131844"},"language":"en","primary_location":{"id":"doi:10.1145/2382564.2382565","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2382564.2382565","pdf_url":null,"source":{"id":"https://openalex.org/S2764465379","display_name":"ACM Transactions on Computing Education","issn_l":"1946-6226","issn":["1946-6226"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Computing Education","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5104706884","display_name":"Khaled Benkrid","orcid":null},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Khaled Benkrid","raw_affiliation_strings":["University of Edinburgh"],"affiliations":[{"raw_affiliation_string":"University of Edinburgh","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006623687","display_name":"Thomas Clayton","orcid":null},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Thomas Clayton","raw_affiliation_strings":["University of Edinburgh"],"affiliations":[{"raw_affiliation_string":"University of Edinburgh","institution_ids":["https://openalex.org/I98677209"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5104706884"],"corresponding_institution_ids":["https://openalex.org/I98677209"],"apc_list":null,"apc_paid":null,"fwci":1.5303,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.83544896,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":95,"max":97},"biblio":{"volume":"12","issue":"4","first_page":"1","last_page":"20"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.724807858467102},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6898739337921143},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5531396865844727},{"id":"https://openalex.org/keywords/curriculum","display_name":"Curriculum","score":0.5234122276306152},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5225943326950073},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5136565566062927},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.49944472312927246},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.41665223240852356},{"id":"https://openalex.org/keywords/multimedia","display_name":"Multimedia","score":0.39811253547668457},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.37303635478019714},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3462202548980713},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34619802236557007},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.13704031705856323},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10709133744239807}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.724807858467102},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6898739337921143},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5531396865844727},{"id":"https://openalex.org/C47177190","wikidata":"https://www.wikidata.org/wiki/Q207137","display_name":"Curriculum","level":2,"score":0.5234122276306152},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5225943326950073},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5136565566062927},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.49944472312927246},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.41665223240852356},{"id":"https://openalex.org/C49774154","wikidata":"https://www.wikidata.org/wiki/Q131765","display_name":"Multimedia","level":1,"score":0.39811253547668457},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.37303635478019714},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3462202548980713},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34619802236557007},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.13704031705856323},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10709133744239807},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C15744967","wikidata":"https://www.wikidata.org/wiki/Q9418","display_name":"Psychology","level":0,"score":0.0},{"id":"https://openalex.org/C19417346","wikidata":"https://www.wikidata.org/wiki/Q7922","display_name":"Pedagogy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2382564.2382565","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2382564.2382565","pdf_url":null,"source":{"id":"https://openalex.org/S2764465379","display_name":"ACM Transactions on Computing Education","issn_l":"1946-6226","issn":["1946-6226"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Computing Education","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.44999998807907104}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W186840447","https://openalex.org/W564382181","https://openalex.org/W1481704255","https://openalex.org/W1482806262","https://openalex.org/W1547209402","https://openalex.org/W1580749063","https://openalex.org/W1732326074","https://openalex.org/W2019527534","https://openalex.org/W2021229554","https://openalex.org/W2116817443","https://openalex.org/W2123160615","https://openalex.org/W2126416764","https://openalex.org/W2128887285","https://openalex.org/W2129334414","https://openalex.org/W2149634175","https://openalex.org/W2170644967","https://openalex.org/W2337068785","https://openalex.org/W2798312797","https://openalex.org/W3128942091","https://openalex.org/W3217611625","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2362523726","https://openalex.org/W2362791631","https://openalex.org/W3015039984","https://openalex.org/W2393133202","https://openalex.org/W2913355112","https://openalex.org/W2378162225","https://openalex.org/W1561512389","https://openalex.org/W2361654132","https://openalex.org/W2366958337","https://openalex.org/W2369375926"],"abstract_inverted_index":{"This":[0,44],"article":[1,85],"presents":[2,86],"the":[3,18,23,53,57,66,80,84,87,132,169,181,190,193],"design":[4,15,72,89,96,133],"and":[5,42,59,74,90,118,142,145,160,177],"implementation":[6,91,122],"of":[7,11,20,25,56,68,79,92,126,134,153,171,180,192],"a":[8],"complete":[9],"review":[10],"undergraduate":[12],"digital":[13,70,94,105],"hardware":[14,71,95,116],"teaching":[16,67,141],"in":[17,33,52,76,131,155],"School":[19],"Engineering":[21],"at":[22],"University":[24],"Edinburgh.":[26],"Four":[27],"guiding":[28],"principles":[29],"have":[30],"been":[31],"used":[32],"this":[34,135,172],"exercise:":[35],"learning-outcome":[36],"driven":[37],"teaching,":[38],"deep":[39],"learning,":[40],"affordability,":[41],"flexibility.":[43],"has":[45],"identified":[46],"discrete":[47],"electronics":[48],"as":[49,61,120],"key":[50],"components":[51],"early":[54],"stages":[55,78],"curriculum":[58],"FPGAs":[60,119],"an":[62,121,178],"economical":[63],"platform":[64],"for":[65,115],"various":[69],"concepts":[73],"techniques":[75],"later":[77],"curriculum.":[81],"In":[82],"particular,":[83],"detailed":[88],"one":[93],"laboratory,":[97],"called":[98],"Gateway,":[99],"which":[100],"introduces":[101],"students":[102],"to":[103,185],"synchronous":[104],"circuit":[106],"development":[107],"from":[108],"high":[109],"level":[110],"functional":[111],"specifications,":[112],"uses":[113],"Verilog":[114],"description":[117],"platform.":[123],"Biggs\u2019":[124],"theory":[125],"constructive":[127],"alignment":[128],"was":[129,174],"applied":[130],"lab\u2019s":[136],"learning":[137,143],"outcomes,":[138],"lab":[139,149,157,173,182,187],"content,":[140],"methods,":[144],"assessment":[146],"methods.":[147],"The":[148],"makes":[150],"extensive":[151],"use":[152],"multimedia":[154],"both":[156],"content":[158],"delivery":[159],"demonstration":[161],"applications":[162],"developed":[163],"by":[164],"students.":[165],"Student":[166],"feedback":[167],"following":[168],"deployment":[170],"overwhelmingly":[175],"positive":[176],"evaluation":[179],"results":[183],"compared":[184],"previous":[186],"offerings\u2019":[188],"shows":[189],"merit":[191],"approach":[194],"taken.":[195]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2015,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}