{"id":"https://openalex.org/W2037134348","doi":"https://doi.org/10.1145/2370816.2370895","title":"Speculative dynamic vectorization for HW/SW co-designed processors","display_name":"Speculative dynamic vectorization for HW/SW co-designed processors","publication_year":2012,"publication_date":"2012-09-19","ids":{"openalex":"https://openalex.org/W2037134348","doi":"https://doi.org/10.1145/2370816.2370895","mag":"2037134348"},"language":"en","primary_location":{"id":"doi:10.1145/2370816.2370895","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2370816.2370895","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st international conference on Parallel architectures and compilation techniques","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://www.research.ed.ac.uk/en/publications/d08287f6-e946-4301-a089-3719974b20b9","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5017675158","display_name":"Rakesh Kumar","orcid":"https://orcid.org/0000-0001-6306-304X"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Rakesh Kumar","raw_affiliation_strings":["Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100731047","display_name":"A. Mart\u00ednez","orcid":"https://orcid.org/0000-0001-8292-0377"},"institutions":[{"id":"https://openalex.org/I4210136471","display_name":"FC Barcelona","ror":"https://ror.org/04bpz1v84","country_code":"ES","type":"other","lineage":["https://openalex.org/I4210136471"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Alejandro Mart\u00ednez","raw_affiliation_strings":["Intel Barcelona Research Center, Intel Labs, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"Intel Barcelona Research Center, Intel Labs, Barcelona, Spain","institution_ids":["https://openalex.org/I4210136471"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100733331","display_name":"Antonio Gonz\u00e1lez","orcid":"https://orcid.org/0000-0002-0009-0996"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Antonio Gonz\u00e1lez","raw_affiliation_strings":["Intel Barcelona Research Center, Intel Labs - UPC, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"Intel Barcelona Research Center, Intel Labs - UPC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5017675158"],"corresponding_institution_ids":["https://openalex.org/I9617848"],"apc_list":null,"apc_paid":null,"fwci":0.8702,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.73130972,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"459","last_page":"460"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9753999710083008,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vectorization","display_name":"Vectorization (mathematics)","score":0.9194568991661072},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7911843061447144},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7086902260780334},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5385943055152893},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41579461097717285},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37192022800445557},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.17553016543388367}],"concepts":[{"id":"https://openalex.org/C41681595","wikidata":"https://www.wikidata.org/wiki/Q7917855","display_name":"Vectorization (mathematics)","level":2,"score":0.9194568991661072},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7911843061447144},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7086902260780334},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5385943055152893},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41579461097717285},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37192022800445557},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.17553016543388367}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/2370816.2370895","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2370816.2370895","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st international conference on Parallel architectures and compilation techniques","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.ed.ac.uk:openaire/d08287f6-e946-4301-a089-3719974b20b9","is_oa":true,"landing_page_url":"https://www.research.ed.ac.uk/en/publications/d08287f6-e946-4301-a089-3719974b20b9","pdf_url":null,"source":{"id":"https://openalex.org/S4406922455","display_name":"Edinburgh Research Explorer","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Kumar, R, Mart\u00ednez, A & Gonz\u00e1lez, A 2012, Speculative Dynamic Vectorization for HW/SW Co-designed Processors. in Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques. New York, NY, USA, pp. 459-460. https://doi.org/10.1145/2370816.2370895","raw_type":"contributionToPeriodical"},{"id":"pmh:oai:pure.ed.ac.uk:publications/d08287f6-e946-4301-a089-3719974b20b9","is_oa":false,"landing_page_url":"http://dl.acm.org/citation.cfm?id=2370895","pdf_url":null,"source":{"id":"https://openalex.org/S4406922455","display_name":"Edinburgh Research Explorer","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""}],"best_oa_location":{"id":"pmh:oai:pure.ed.ac.uk:openaire/d08287f6-e946-4301-a089-3719974b20b9","is_oa":true,"landing_page_url":"https://www.research.ed.ac.uk/en/publications/d08287f6-e946-4301-a089-3719974b20b9","pdf_url":null,"source":{"id":"https://openalex.org/S4406922455","display_name":"Edinburgh Research Explorer","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Kumar, R, Mart\u00ednez, A & Gonz\u00e1lez, A 2012, Speculative Dynamic Vectorization for HW/SW Co-designed Processors. in Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques. New York, NY, USA, pp. 459-460. https://doi.org/10.1145/2370816.2370895","raw_type":"contributionToPeriodical"},"sustainable_development_goals":[{"score":0.6100000143051147,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2762467749","https://openalex.org/W2161584192","https://openalex.org/W2374048355","https://openalex.org/W2359910081","https://openalex.org/W2035419609","https://openalex.org/W343461076","https://openalex.org/W2601539487","https://openalex.org/W1881614813","https://openalex.org/W2787898679","https://openalex.org/W2360242203"],"abstract_inverted_index":{"Hardware/Software":[0],"(HW/SW)":[1],"co-designed":[2],"processors":[3,20],"have":[4],"emerged":[5],"as":[6],"a":[7,46],"promising":[8],"solution":[9],"to":[10,24,51],"the":[11,26,32,40],"power":[12],"and":[13],"complexity":[14],"problems":[15],"of":[16,31],"modern":[17],"microprocessors.":[18],"These":[19],"utilize":[21],"dynamic":[22,48],"optimizations":[23],"improve":[25],"performance.":[27],"However,":[28],"vectorization,":[29],"one":[30],"most":[33],"potent":[34],"optimizations,":[35],"has":[36],"not":[37],"yet":[38],"received":[39],"deserved":[41],"attention.":[42],"This":[43],"paper":[44],"presents":[45],"speculative":[47],"vectorization":[49],"algorithm":[50],"explore":[52],"its":[53],"potential.":[54]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
