{"id":"https://openalex.org/W1984891291","doi":"https://doi.org/10.1145/2347655.2347669","title":"Energy-guided exploration of on-chip network design for exa-scale computing","display_name":"Energy-guided exploration of on-chip network design for exa-scale computing","publication_year":2012,"publication_date":"2012-06-03","ids":{"openalex":"https://openalex.org/W1984891291","doi":"https://doi.org/10.1145/2347655.2347669","mag":"1984891291"},"language":"en","primary_location":{"id":"doi:10.1145/2347655.2347669","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2347655.2347669","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Workshop on System Level Interconnect Prediction","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084255924","display_name":"\u00dcmit Y. Ogras","orcid":"https://orcid.org/0000-0002-5045-5535"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Umit Y. Ogras","raw_affiliation_strings":["Strategic CAD Labs, Intel Corporation","Strategic CAD Lab, Intel Corporation#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Strategic CAD Labs, Intel Corporation","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Strategic CAD Lab, Intel Corporation#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078556358","display_name":"Yunus Emre","orcid":null},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yunus Emre","raw_affiliation_strings":["Arizona State University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Arizona State University","institution_ids":["https://openalex.org/I55732556"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102143692","display_name":"Jianping Xu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jianping Xu","raw_affiliation_strings":["Intel Labs, Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Labs, Intel Corporation","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019748531","display_name":"Timothy Kam","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Timothy Kam","raw_affiliation_strings":["Strategic CAD Labs, Intel Corporation","Strategic CAD Lab, Intel Corporation#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Strategic CAD Labs, Intel Corporation","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Strategic CAD Lab, Intel Corporation#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007256099","display_name":"Michael Kishinevsky","orcid":"https://orcid.org/0000-0002-5593-9694"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Kishinevsky","raw_affiliation_strings":["Strategic CAD Labs, Intel Corporation","Strategic CAD Lab, Intel Corporation#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Strategic CAD Labs, Intel Corporation","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Strategic CAD Lab, Intel Corporation#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.10431974,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"24","last_page":"31"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8094735741615295},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7080461978912354},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.6553196310997009},{"id":"https://openalex.org/keywords/testbed","display_name":"Testbed","score":0.622876763343811},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5910509824752808},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.583494246006012},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.5685321092605591},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5289901494979858},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5086589455604553},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4652019441127777},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.46178725361824036},{"id":"https://openalex.org/keywords/exascale-computing","display_name":"Exascale computing","score":0.4393686354160309},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.43878403306007385},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.43227052688598633},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.428791344165802},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.4167725443840027},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3769091069698334},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.3111688494682312},{"id":"https://openalex.org/keywords/supercomputer","display_name":"Supercomputer","score":0.296359658241272},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1986897587776184},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1400063931941986},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.10189968347549438},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08155739307403564}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8094735741615295},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7080461978912354},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.6553196310997009},{"id":"https://openalex.org/C31395832","wikidata":"https://www.wikidata.org/wiki/Q1318674","display_name":"Testbed","level":2,"score":0.622876763343811},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5910509824752808},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.583494246006012},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.5685321092605591},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5289901494979858},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5086589455604553},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4652019441127777},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.46178725361824036},{"id":"https://openalex.org/C2778837361","wikidata":"https://www.wikidata.org/wiki/Q2450880","display_name":"Exascale computing","level":3,"score":0.4393686354160309},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.43878403306007385},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.43227052688598633},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.428791344165802},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.4167725443840027},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3769091069698334},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3111688494682312},{"id":"https://openalex.org/C83283714","wikidata":"https://www.wikidata.org/wiki/Q121117","display_name":"Supercomputer","level":2,"score":0.296359658241272},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1986897587776184},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1400063931941986},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.10189968347549438},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08155739307403564},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2347655.2347669","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2347655.2347669","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Workshop on System Level Interconnect Prediction","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1837653564","https://openalex.org/W2005897603","https://openalex.org/W2006500015","https://openalex.org/W2036135729","https://openalex.org/W2048789167","https://openalex.org/W2095314640","https://openalex.org/W2098156582","https://openalex.org/W2099952176","https://openalex.org/W2103066735","https://openalex.org/W2107299528","https://openalex.org/W2116861063","https://openalex.org/W2117324528","https://openalex.org/W2140834004","https://openalex.org/W2145252892","https://openalex.org/W2149212714","https://openalex.org/W2155371841","https://openalex.org/W2161773701","https://openalex.org/W2166151045","https://openalex.org/W4220666134","https://openalex.org/W4244034697","https://openalex.org/W6638708518"],"related_works":["https://openalex.org/W1616582327","https://openalex.org/W1534227216","https://openalex.org/W2980362785","https://openalex.org/W1970143103","https://openalex.org/W2159120180","https://openalex.org/W2979921829","https://openalex.org/W2116283643","https://openalex.org/W2735793669","https://openalex.org/W2123478829","https://openalex.org/W2132949691"],"abstract_inverted_index":{"Designing":[0],"energy-efficient":[1,59],"systems":[2,83],"under":[3],"tight":[4],"performance":[5,61],"and":[6,24,75,103,114],"energy":[7,28],"constraints":[8],"becomes":[9],"increasingly":[10],"challenging":[11],"for":[12,81,130],"exascale":[13,82],"computing.":[14,62],"In":[15,93],"particular,":[16,94],"interconnecting":[17],"hundreds":[18],"of":[19,66,86,91,133],"cores,":[20],"caches,":[21],"integrated":[22],"memory":[23,112,117],"I/O":[25],"controllers":[26],"in":[27,51,88],"efficient":[29],"way":[30],"stands":[31],"out":[32],"as":[33,54],"a":[34,55,73,97,127],"new":[35],"challenge.":[36],"This":[37],"paper":[38],"proposes":[39],"hierarchical":[40,67,134],"on-chip":[41],"networks":[42],"that":[43],"take":[44],"the":[45,49,89,120],"proximity":[46],"advantage":[47],"between":[48],"cores":[50,87],"smaller":[52],"clusters":[53],"promising":[56],"approach":[57],"toward":[58],"high":[60],"The":[63],"design":[64,77],"trade-offs":[65],"interconnect":[68],"architectures":[69],"are":[70],"studied":[71],"using":[72],"fast":[74],"scalable":[76],"space":[78],"exploration":[79,132],"tool":[80],"with":[84,99],"number":[85],"order":[90],"thousands.":[92],"we":[95],"consider":[96],"system":[98,122],"720":[100],"processing":[101],"nodes":[102],"two-level":[104],"network":[105],"hierarchy.":[106],"By":[107],"supporting":[108],"both":[109],"traditional":[110],"cache-based":[111],"model":[113],"scratch":[115],"pad":[116],"(SPM)":[118],"model,":[119],"target":[121],"architecture":[123],"proves":[124],"to":[125],"be":[126],"good":[128],"testbed":[129],"energy-guided":[131],"networks.":[135]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
