{"id":"https://openalex.org/W1990635183","doi":"https://doi.org/10.1145/2335755.2335797","title":"A systematic process for efficient execution on Intel's heterogeneous computation nodes","display_name":"A systematic process for efficient execution on Intel's heterogeneous computation nodes","publication_year":2012,"publication_date":"2012-07-16","ids":{"openalex":"https://openalex.org/W1990635183","doi":"https://doi.org/10.1145/2335755.2335797","mag":"1990635183"},"language":"en","primary_location":{"id":"doi:10.1145/2335755.2335797","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2335755.2335797","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 1st Conference of the Extreme Science and Engineering Discovery Environment: Bridging from the eXtreme to the campus and beyond","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002648554","display_name":"Ashay Rane","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ashay Rane","raw_affiliation_strings":["TACC, The University of Texas at Austin"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TACC, The University of Texas at Austin","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064263297","display_name":"James C. Browne","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James Browne","raw_affiliation_strings":["The University of Texas at Austin","The University of Texas, at Austin"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Texas at Austin","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"The University of Texas, at Austin","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034083304","display_name":"Lars Koesterke","orcid":"https://orcid.org/0000-0003-3455-4565"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lars Koesterke","raw_affiliation_strings":["TACC, The University of Texas at Austin"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TACC, The University of Texas at Austin","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05910574,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8601234555244446},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.7964265942573547},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7302805185317993},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.680952787399292},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.49247822165489197},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4784948229789734},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4783993661403656},{"id":"https://openalex.org/keywords/xeon-phi","display_name":"Xeon Phi","score":0.463054895401001},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.44622910022735596},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.4447590708732605},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.43938249349594116},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.4346485435962677},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.4340100586414337},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.42653244733810425},{"id":"https://openalex.org/keywords/process-migration","display_name":"Process migration","score":0.4163922071456909},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.29398947954177856},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2415393590927124},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.1456322968006134},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09370076656341553}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8601234555244446},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.7964265942573547},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7302805185317993},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.680952787399292},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.49247822165489197},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4784948229789734},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4783993661403656},{"id":"https://openalex.org/C96972482","wikidata":"https://www.wikidata.org/wiki/Q1049168","display_name":"Xeon Phi","level":2,"score":0.463054895401001},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.44622910022735596},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.4447590708732605},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.43938249349594116},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4346485435962677},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.4340100586414337},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.42653244733810425},{"id":"https://openalex.org/C36351404","wikidata":"https://www.wikidata.org/wiki/Q7247295","display_name":"Process migration","level":3,"score":0.4163922071456909},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.29398947954177856},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2415393590927124},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.1456322968006134},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09370076656341553},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2335755.2335797","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2335755.2335797","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 1st Conference of the Extreme Science and Engineering Discovery Environment: Bridging from the eXtreme to the campus and beyond","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2295535512","display_name":null,"funder_award_id":"OCI 0622780","funder_id":"https://openalex.org/F4320337377","funder_display_name":"Office of Advanced Cyberinfrastructure"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320309480","display_name":"Nvidia","ror":"https://ror.org/03jdj4y14"},{"id":"https://openalex.org/F4320337377","display_name":"Office of Advanced Cyberinfrastructure","ror":"https://ror.org/04nh1dc89"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1782174992","https://openalex.org/W1981896890","https://openalex.org/W2019560741","https://openalex.org/W2028798345","https://openalex.org/W2037243806","https://openalex.org/W2043218878","https://openalex.org/W2045598937","https://openalex.org/W2064541493","https://openalex.org/W2080592089","https://openalex.org/W2126026097","https://openalex.org/W6661898889"],"related_works":["https://openalex.org/W2505067803","https://openalex.org/W1634740951","https://openalex.org/W2148563915","https://openalex.org/W2807092481","https://openalex.org/W2022666014","https://openalex.org/W2337418885","https://openalex.org/W4207012101","https://openalex.org/W1581876376","https://openalex.org/W2604252333","https://openalex.org/W90144894"],"abstract_inverted_index":{"Heterogeneous":[0],"architectures":[1],"(mainstream":[2],"CPUs":[3],"with":[4,21,34],"accelerators/co-processors)":[5],"are":[6,67],"expected":[7],"to":[8,49,58,168],"become":[9],"more":[10,123],"prevalent":[11],"in":[12,105],"high":[13],"performance":[14],"computing":[15],"clusters.":[16],"This":[17,134],"paper":[18,135],"deals":[19],"specifically":[20],"attaining":[22],"efficient":[23],"execution":[24,65,143,199],"on":[25,125,130,140,144,158,200],"nodes":[26,47],"which":[27,148,152],"combine":[28],"Intel's":[29,44],"multicore":[30,56,132,146],"Sandy":[31],"Bridge":[32],"chips":[33,57,61,72,88,161],"MIC":[35,198],"manycore":[36,71,87,127,160],"chips.":[37],"The":[38,178],"architecture":[39],"and":[40,93,101,162,164,176,192],"software":[41],"stack":[42],"for":[43,197],"heterogeneous":[45],"computation":[46,204],"attempt":[48],"make":[50],"migration":[51],"from":[52],"the":[53,59,78,112,126,131,159,181,189],"now":[54],"common":[55],"many-core":[60],"straightforward.":[62],"However,":[63],"specific":[64,190],"characteristics":[66],"favored":[68],"by":[69,185],"these":[70],"such":[73],"as":[74,102],"making":[75],"use":[76],"of":[77,118,142,180,188],"wider":[79],"vector":[80],"instructions,":[81],"minimal":[82],"inter-thread":[83],"conflicts,":[84],"etc.":[85],"Additionally":[86],"have":[89],"lower":[90],"clock":[91],"speed":[92],"no":[94],"unified":[95],"last-level":[96],"cache.":[97],"As":[98],"a":[99,137,201],"result,":[100],"we":[103],"demonstrate":[104],"this":[106],"paper,":[107],"it":[108],"will":[109,121,155],"commonly":[110],"be":[111],"case":[113],"that":[114,194],"not":[115],"all":[116],"parts":[117],"an":[119],"application":[120,167],"execute":[122,156],"efficiently":[124,157],"chip":[128],"than":[129],"chip.":[133],"presents":[136],"process,":[138],"based":[139],"measurements":[141],"Westmere-based":[145],"chips,":[147],"can":[149],"accurately":[150],"predict":[151],"code":[153],"segments":[154],"illustrates":[163],"evaluates":[165],"its":[166],"three":[169],"substantial":[170],"full":[171],"programs":[172],"--":[173],"HOMME,":[174],"MOIL":[175],"MILC.":[177],"effectiveness":[179],"process":[182],"is":[183],"validated":[184],"verifying":[186],"scalability":[187],"functions":[191],"loops":[193],"were":[195],"recommended":[196],"Knights":[202],"Ferry":[203],"node.":[205]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}