{"id":"https://openalex.org/W4241660839","doi":"https://doi.org/10.1145/228370","title":"Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays - FPGA '96","display_name":"Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays - FPGA '96","publication_year":1996,"publication_date":"1996-01-01","ids":{"openalex":"https://openalex.org/W4241660839","doi":"https://doi.org/10.1145/228370"},"language":"en","primary_location":{"id":"doi:10.1145/228370","is_oa":false,"landing_page_url":"https://doi.org/10.1145/228370","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":null,"raw_type":"proceedings"},"type":"paratext","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":true,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.8765000104904175,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.8765000104904175,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.7846999764442444,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.7757999897003174,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8796646595001221},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5380536913871765},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.48340287804603577},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.4822417199611664},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.41446322202682495},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.32749438285827637},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3236996531486511},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.30587488412857056},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.23265081644058228},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.19276422262191772},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.041311562061309814}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8796646595001221},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5380536913871765},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.48340287804603577},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.4822417199611664},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.41446322202682495},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.32749438285827637},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3236996531486511},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.30587488412857056},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.23265081644058228},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.19276422262191772},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.041311562061309814}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/228370","is_oa":false,"landing_page_url":"https://doi.org/10.1145/228370","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":null,"raw_type":"proceedings"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2014165129","https://openalex.org/W2466591189","https://openalex.org/W1972395546","https://openalex.org/W2052520871","https://openalex.org/W3163714531","https://openalex.org/W594316872","https://openalex.org/W3047339307","https://openalex.org/W3034517114","https://openalex.org/W3139819943","https://openalex.org/W2794692675"],"abstract_inverted_index":null,"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":6}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}