{"id":"https://openalex.org/W2157541699","doi":"https://doi.org/10.1145/2228360.2228442","title":"Guiding a physical design closure system to produce easier-to-route designs with more predictable timing","display_name":"Guiding a physical design closure system to produce easier-to-route designs with more predictable timing","publication_year":2012,"publication_date":"2012-05-31","ids":{"openalex":"https://openalex.org/W2157541699","doi":"https://doi.org/10.1145/2228360.2228442","mag":"2157541699"},"language":"en","primary_location":{"id":"doi:10.1145/2228360.2228442","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2228360.2228442","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 49th Annual Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100448026","display_name":"Zhuo Li","orcid":"https://orcid.org/0000-0002-5535-5920"},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Zhuo Li","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, TX"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, TX","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113656006","display_name":"Charles J. Alpert","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Charles J. Alpert","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, TX"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, TX","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043138186","display_name":"Gi-Joon Nam","orcid":"https://orcid.org/0000-0001-6355-2935"},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gi-Joon Nam","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, TX"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, TX","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111686227","display_name":"Cliff Sze","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cliff Sze","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, TX"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, TX","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089395977","display_name":"V. Natarajan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Natarajan Viswanathan","raw_affiliation_strings":["IBM Systems &amp; Technology Group, Austin, TX"],"affiliations":[{"raw_affiliation_string":"IBM Systems &amp; Technology Group, Austin, TX","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074662629","display_name":"Nancy Y. Zhou","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Nancy Y. Zhou","raw_affiliation_strings":["IBM Systems &amp; Technology Group, Austin, TX"],"affiliations":[{"raw_affiliation_string":"IBM Systems &amp; Technology Group, Austin, TX","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5100448026"],"corresponding_institution_ids":["https://openalex.org/I4210156936"],"apc_list":null,"apc_paid":null,"fwci":2.4919,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.90251049,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"465","last_page":"470"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.9331055879592896},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.822262167930603},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7310582399368286},{"id":"https://openalex.org/keywords/steiner-tree-problem","display_name":"Steiner tree problem","score":0.7147468328475952},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6949271559715271},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.5950286388397217},{"id":"https://openalex.org/keywords/closure","display_name":"Closure (psychology)","score":0.5257580876350403},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5235933065414429},{"id":"https://openalex.org/keywords/network-routing","display_name":"Network routing","score":0.514360785484314},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5014979839324951},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4970426857471466},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4850022494792938},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4319442808628082},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.34739935398101807},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.306312620639801},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.26284259557724},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.18359848856925964},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.18315532803535461},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.1630810797214508},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.11826682090759277},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1137935221195221},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1097845733165741}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.9331055879592896},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.822262167930603},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7310582399368286},{"id":"https://openalex.org/C76220878","wikidata":"https://www.wikidata.org/wiki/Q1764144","display_name":"Steiner tree problem","level":2,"score":0.7147468328475952},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6949271559715271},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.5950286388397217},{"id":"https://openalex.org/C146834321","wikidata":"https://www.wikidata.org/wiki/Q2979672","display_name":"Closure (psychology)","level":2,"score":0.5257580876350403},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5235933065414429},{"id":"https://openalex.org/C2983435990","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Network routing","level":3,"score":0.514360785484314},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5014979839324951},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4970426857471466},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4850022494792938},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4319442808628082},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.34739935398101807},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.306312620639801},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.26284259557724},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.18359848856925964},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.18315532803535461},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.1630810797214508},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.11826682090759277},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1137935221195221},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1097845733165741},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C34447519","wikidata":"https://www.wikidata.org/wiki/Q179522","display_name":"Market economy","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2228360.2228442","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2228360.2228442","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 49th Annual Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":37,"referenced_works":["https://openalex.org/W1550550617","https://openalex.org/W1970795504","https://openalex.org/W1973505932","https://openalex.org/W1978226299","https://openalex.org/W1982924274","https://openalex.org/W1999116995","https://openalex.org/W1999938868","https://openalex.org/W2003145440","https://openalex.org/W2010747748","https://openalex.org/W2010952387","https://openalex.org/W2011912079","https://openalex.org/W2025939442","https://openalex.org/W2038987112","https://openalex.org/W2043643711","https://openalex.org/W2049546399","https://openalex.org/W2050219435","https://openalex.org/W2051611158","https://openalex.org/W2063006063","https://openalex.org/W2072175262","https://openalex.org/W2080409033","https://openalex.org/W2083418180","https://openalex.org/W2096117010","https://openalex.org/W2096970935","https://openalex.org/W2097452558","https://openalex.org/W2103848222","https://openalex.org/W2113109796","https://openalex.org/W2118412523","https://openalex.org/W2125831674","https://openalex.org/W2127434816","https://openalex.org/W2133171792","https://openalex.org/W2133435384","https://openalex.org/W2141185123","https://openalex.org/W2162756981","https://openalex.org/W2167730834","https://openalex.org/W2167841124","https://openalex.org/W2168611993","https://openalex.org/W2170957689"],"related_works":["https://openalex.org/W1995821058","https://openalex.org/W3129822007","https://openalex.org/W146048418","https://openalex.org/W4386859294","https://openalex.org/W1557016741","https://openalex.org/W2157541699","https://openalex.org/W2077246255","https://openalex.org/W2126475478","https://openalex.org/W2160966597","https://openalex.org/W2543290882"],"abstract_inverted_index":{"Physical":[0],"synthesis":[1,19,60],"has":[2],"emerged":[3],"as":[4],"one":[5],"of":[6,124],"the":[7,17,31,75,133,157],"most":[8],"important":[9],"tools":[10],"in":[11,37],"design":[12,65,89,95,135],"closure,":[13],"which":[14],"starts":[15],"with":[16,53,67,74,83],"logic":[18],"step":[20],"and":[21,27,46,55,93,107,131],"generates":[22],"a":[23,41,113,122],"new":[24],"optimized":[25],"netlist":[26],"its":[28],"layout":[29],"for":[30,97],"final":[32],"signoff":[33],"process.":[34],"As":[35],"stated":[36],"[1],":[38],"\"it":[39],"is":[40],"wrapper":[42],"around":[43],"traditional":[44,58],"place":[45],"route,":[47],"whereby":[48],"synthesis-based":[49],"optimization":[50],"are":[51,153],"interwoven":[52],"placement":[54],"routing.\"":[56],"A":[57],"physical":[59,134],"tool":[61],"generally":[62],"focuses":[63],"on":[64],"closure":[66,136],"Steiner":[68,85],"wire":[69],"model.":[70],"It":[71],"optimizes":[72],"timing/area/power":[73],"assumption":[76],"that":[77,126],"each":[78],"net":[79],"can":[80],"be":[81],"routed":[82],"optimal":[84],"tree.":[86],"However,":[87],"advanced":[88],"rules,":[90],"more":[91,115],"IP":[92],"hierarchical":[94],"styles":[96],"super-large":[98],"billion-gate":[99],"designs,":[100,145],"serious":[101],"buffering":[102],"problems":[103],"from":[104],"interconnect":[105],"scaling":[106],"metal":[108],"layer":[109],"stacks":[110],"make":[111],"routing":[112],"much":[114],"challenging":[116],"problem":[117],"[2].":[118],"This":[119],"paper":[120],"discusses":[121],"series":[123],"techniques":[125],"may":[127],"relieve":[128],"this":[129],"problem,":[130],"guide":[132],"system":[137],"to":[138,143],"produce":[139],"not":[140],"only":[141],"easier":[142],"route":[144],"but":[146],"also":[147,154],"better":[148],"timing":[149],"quality.":[150],"Open":[151],"challenges":[152],"overviewed":[155],"at":[156],"end.":[158]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":1}],"updated_date":"2026-03-13T16:22:10.518609","created_date":"2025-10-10T00:00:00"}
