{"id":"https://openalex.org/W2033855210","doi":"https://doi.org/10.1145/2209291.2209294","title":"A full lifecycle performance verification methodology for multicore systems-on-chip","display_name":"A full lifecycle performance verification methodology for multicore systems-on-chip","publication_year":2012,"publication_date":"2012-06-01","ids":{"openalex":"https://openalex.org/W2033855210","doi":"https://doi.org/10.1145/2209291.2209294","mag":"2033855210"},"language":"en","primary_location":{"id":"doi:10.1145/2209291.2209294","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2209291.2209294","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113591675","display_name":"Jim Holt","orcid":null},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jim Holt","raw_affiliation_strings":["Freescale Semiconductor, Inc. & Massachusetts Institute of Technology","Freescale Semiconductor, Inc. & Massachusetts Institute of Technology#TAB#"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Inc. & Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]},{"raw_affiliation_string":"Freescale Semiconductor, Inc. & Massachusetts Institute of Technology#TAB#","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050847957","display_name":"Jaideep Dastidar","orcid":"https://orcid.org/0000-0003-4851-3350"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jaideep Dastidar","raw_affiliation_strings":["Freescale Semiconductor, Inc., Austin, Texas","Freescale Semiconductor, Inc., Austin, Texas#TAB#"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Inc., Austin, Texas","institution_ids":[]},{"raw_affiliation_string":"Freescale Semiconductor, Inc., Austin, Texas#TAB#","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082130454","display_name":"David Lindberg","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"David Lindberg","raw_affiliation_strings":["Freescale Semiconductor, Inc., Austin, Texas","Freescale Semiconductor, Inc., Austin, Texas#TAB#"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Inc., Austin, Texas","institution_ids":[]},{"raw_affiliation_string":"Freescale Semiconductor, Inc., Austin, Texas#TAB#","institution_ids":[]}]},{"author_position":"middle","author":{"id":null,"display_name":"John Pape","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"John Pape","raw_affiliation_strings":["Freescale Semiconductor, Inc., Austin, Texas","Freescale Semiconductor, Inc., Austin, Texas#TAB#"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Inc., Austin, Texas","institution_ids":[]},{"raw_affiliation_string":"Freescale Semiconductor, Inc., Austin, Texas#TAB#","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109108275","display_name":"Peng Yang","orcid":"https://orcid.org/0009-0001-3592-3740"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Peng Yang","raw_affiliation_strings":["Freescale Semiconductor, Inc., Austin, Texas","Freescale Semiconductor, Inc., Austin, Texas#TAB#"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Inc., Austin, Texas","institution_ids":[]},{"raw_affiliation_string":"Freescale Semiconductor, Inc., Austin, Texas#TAB#","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5113591675"],"corresponding_institution_ids":["https://openalex.org/I63966007"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.1054631,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"17","issue":"3","first_page":"1","last_page":"18"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8834643959999084},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.6856574416160583},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.6833522319793701},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.6121950745582581},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5236368179321289},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.506241500377655},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.4841383397579193},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.47388026118278503},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4600202441215515},{"id":"https://openalex.org/keywords/limiting","display_name":"Limiting","score":0.42343661189079285},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.4128414988517761},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40874940156936646},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.3956061005592346},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17858636379241943},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.1736568808555603},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.1424292027950287},{"id":"https://openalex.org/keywords/software-system","display_name":"Software system","score":0.11263039708137512},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10540822148323059}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8834643959999084},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.6856574416160583},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6833522319793701},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.6121950745582581},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5236368179321289},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.506241500377655},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.4841383397579193},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.47388026118278503},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4600202441215515},{"id":"https://openalex.org/C188198153","wikidata":"https://www.wikidata.org/wiki/Q1613840","display_name":"Limiting","level":2,"score":0.42343661189079285},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.4128414988517761},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40874940156936646},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.3956061005592346},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17858636379241943},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.1736568808555603},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.1424292027950287},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.11263039708137512},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10540822148323059},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2209291.2209294","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2209291.2209294","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","display_name":"Decent work and economic growth","score":0.4000000059604645}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1942802553","https://openalex.org/W1963527702","https://openalex.org/W1982330718","https://openalex.org/W1985418406","https://openalex.org/W1990262300","https://openalex.org/W1997998060","https://openalex.org/W2011900848","https://openalex.org/W2017503457","https://openalex.org/W2041129851","https://openalex.org/W2098180992","https://openalex.org/W2103897623","https://openalex.org/W2105321788","https://openalex.org/W2115345006","https://openalex.org/W2119543864","https://openalex.org/W2122593349","https://openalex.org/W2128761774","https://openalex.org/W2139653418","https://openalex.org/W2145930857","https://openalex.org/W2150347868","https://openalex.org/W2158291854","https://openalex.org/W2163536899","https://openalex.org/W2165722080","https://openalex.org/W2172003873","https://openalex.org/W2538315158","https://openalex.org/W4242827347","https://openalex.org/W4256575237"],"related_works":["https://openalex.org/W3120172095","https://openalex.org/W2105593427","https://openalex.org/W2153955347","https://openalex.org/W2106507440","https://openalex.org/W1928822090","https://openalex.org/W2118572231","https://openalex.org/W4375857205","https://openalex.org/W3036403349","https://openalex.org/W2108860137","https://openalex.org/W2535719568"],"abstract_inverted_index":{"Multicore":[0],"Systems-on-Chip":[1],"(MCSoC)":[2],"are":[3],"comprised":[4],"of":[5,9,20,55,94,110,126,136],"a":[6,25,59],"rich":[7],"set":[8],"processor":[10],"cores,":[11],"specialized":[12],"hardware":[13],"accelerators,":[14],"and":[15,27,106,143,153],"I/O":[16],"interfaces.":[17],"Functional":[18],"verification":[19,35,78,125,139],"these":[21],"complex":[22],"designs":[23],"is":[24,36,50,87,114],"critical":[26],"demanding":[28],"task,":[29],"however,":[30],"focusing":[31],"only":[32],"on":[33,103],"functional":[34],"very":[37],"risky":[38],"because":[39],"the":[40,47,72,92,104,108,147,150],"motivation":[41],"for":[42,155],"building":[43],"such":[44],"systems":[45],"in":[46,71,85],"first":[48],"place":[49],"to":[51,80],"achieve":[52],"high":[53],"levels":[54],"system":[56,83],"throughput.":[57],"Therefore":[58],"functionally":[60],"correct":[61],"MCSoC":[62,137],"that":[63,98,113],"does":[64],"not":[65],"exhibit":[66],"sufficient":[67],"performance":[68,77,124,138],"will":[69],"fail":[70],"market.":[73],"In":[74],"addition,":[75],"limiting":[76],"efforts":[79],"analyzing":[81],"individual":[82],"components":[84],"isolation":[86],"insufficient":[88],"due":[89],"to:":[90],"(1)":[91],"degree":[93,109],"system-level":[95,123],"resource":[96],"contention":[97],"an":[99,118,131],"application":[100],"domain":[101],"imposes":[102],"MCSoC,":[105],"(2)":[107],"configuration":[111],"flexibility":[112],"typically":[115],"afforded":[116],"by":[117],"MCSoC.":[119,127],"These":[120],"factors":[121],"motivate":[122],"This":[128],"article":[129],"presents":[130],"important":[132],"industrial":[133],"case":[134],"study":[135],"involving":[140],"both":[141],"pre-":[142],"postsilicon":[144],"analysis,":[145],"highlighting":[146],"methodology":[148],"used,":[149],"lessons":[151],"learned,":[152],"recommendations":[154],"improvement.":[156]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2026-04-17T18:11:37.981687","created_date":"2025-10-10T00:00:00"}