{"id":"https://openalex.org/W2138449840","doi":"https://doi.org/10.1145/2206781.2206866","title":"Verilog-AMS-PAM","display_name":"Verilog-AMS-PAM","publication_year":2012,"publication_date":"2012-05-03","ids":{"openalex":"https://openalex.org/W2138449840","doi":"https://doi.org/10.1145/2206781.2206866","mag":"2138449840"},"language":"en","primary_location":{"id":"doi:10.1145/2206781.2206866","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2206781.2206866","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103292239","display_name":"Geng Zheng","orcid":null},"institutions":[{"id":"https://openalex.org/I123534392","display_name":"University of North Texas","ror":"https://ror.org/00v97ad02","country_code":"US","type":"education","lineage":["https://openalex.org/I123534392"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Geng Zheng","raw_affiliation_strings":["University of North Texas, Denton, TX, USA","University of North Texas, Denton, TX, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"University of North Texas, Denton, TX, USA","institution_ids":["https://openalex.org/I123534392"]},{"raw_affiliation_string":"University of North Texas, Denton, TX, USA#TAB#","institution_ids":["https://openalex.org/I123534392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070359867","display_name":"Saraju P. Mohanty","orcid":"https://orcid.org/0000-0003-2959-6541"},"institutions":[{"id":"https://openalex.org/I123534392","display_name":"University of North Texas","ror":"https://ror.org/00v97ad02","country_code":"US","type":"education","lineage":["https://openalex.org/I123534392"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Saraju P. Mohanty","raw_affiliation_strings":["University of North Texas, Denton, TX, USA","University of North Texas, Denton, TX, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"University of North Texas, Denton, TX, USA","institution_ids":["https://openalex.org/I123534392"]},{"raw_affiliation_string":"University of North Texas, Denton, TX, USA#TAB#","institution_ids":["https://openalex.org/I123534392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062843590","display_name":"Elias Kougianos","orcid":"https://orcid.org/0000-0002-1616-7628"},"institutions":[{"id":"https://openalex.org/I123534392","display_name":"University of North Texas","ror":"https://ror.org/00v97ad02","country_code":"US","type":"education","lineage":["https://openalex.org/I123534392"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Elias Kougianos","raw_affiliation_strings":["University of North Texas, Denton, TX, USA","University of North Texas, Denton, TX, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"University of North Texas, Denton, TX, USA","institution_ids":["https://openalex.org/I123534392"]},{"raw_affiliation_string":"University of North Texas, Denton, TX, USA#TAB#","institution_ids":["https://openalex.org/I123534392"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044487544","display_name":"Oleg Garitselov","orcid":null},"institutions":[{"id":"https://openalex.org/I123534392","display_name":"University of North Texas","ror":"https://ror.org/00v97ad02","country_code":"US","type":"education","lineage":["https://openalex.org/I123534392"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Oleg Garitselov","raw_affiliation_strings":["University of North Texas, Denton, TX, USA","University of North Texas, Denton, TX, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"University of North Texas, Denton, TX, USA","institution_ids":["https://openalex.org/I123534392"]},{"raw_affiliation_string":"University of North Texas, Denton, TX, USA#TAB#","institution_ids":["https://openalex.org/I123534392"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5103292239"],"corresponding_institution_ids":["https://openalex.org/I123534392"],"apc_list":null,"apc_paid":null,"fwci":0.2455,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.62246277,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"351","last_page":"356"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8810364007949829},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7286272644996643},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5178342461585999},{"id":"https://openalex.org/keywords/behavioral-modeling","display_name":"Behavioral modeling","score":0.5067830681800842},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.4571615755558014},{"id":"https://openalex.org/keywords/modeling-and-simulation","display_name":"Modeling and simulation","score":0.45125165581703186},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.4202682375907898},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.32883331179618835},{"id":"https://openalex.org/keywords/simulation","display_name":"Simulation","score":0.3279685974121094},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24558645486831665},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.17812380194664001},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10890534520149231}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8810364007949829},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7286272644996643},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5178342461585999},{"id":"https://openalex.org/C78639753","wikidata":"https://www.wikidata.org/wiki/Q3318160","display_name":"Behavioral modeling","level":2,"score":0.5067830681800842},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.4571615755558014},{"id":"https://openalex.org/C167343916","wikidata":"https://www.wikidata.org/wiki/Q6888384","display_name":"Modeling and simulation","level":2,"score":0.45125165581703186},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.4202682375907898},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.32883331179618835},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.3279685974121094},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24558645486831665},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.17812380194664001},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10890534520149231},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2206781.2206866","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2206781.2206866","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8299999833106995}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W566385658","https://openalex.org/W1540085841","https://openalex.org/W1996493662","https://openalex.org/W2038842666","https://openalex.org/W2052507127","https://openalex.org/W2081050856","https://openalex.org/W2101197344","https://openalex.org/W2102525201","https://openalex.org/W2118300011","https://openalex.org/W2122882943","https://openalex.org/W2130471231","https://openalex.org/W2143475396","https://openalex.org/W2152223449","https://openalex.org/W2161332670","https://openalex.org/W2544455909","https://openalex.org/W4205590754"],"related_works":["https://openalex.org/W2139759413","https://openalex.org/W2004826944","https://openalex.org/W1935030095","https://openalex.org/W2411121647","https://openalex.org/W2107240870","https://openalex.org/W2136295006","https://openalex.org/W54894869","https://openalex.org/W2165480138","https://openalex.org/W2162678295","https://openalex.org/W2544421437"],"abstract_inverted_index":{"Current":[0],"Verilog-AMS":[1,58,90],"system":[2],"level":[3,52],"modeling":[4],"does":[5],"not":[6],"capture":[7],"the":[8,14,28,44,76,110,120,138,156],"physical":[9],"design":[10,16,94,102,165],"(layout)":[11],"information":[12,53],"of":[13,30,43,66],"target":[15],"as":[17,73,75],"it":[18],"is":[19,47,70],"meant":[20],"to":[21,98,119],"be":[22,34],"fast":[23,100,162],"behavioral":[24,31,91,129,152],"simulation":[25,32,65,112,163],"only.":[26],"Thus,":[27],"results":[29],"can":[33],"very":[35],"inaccurate.":[36],"In":[37],"this":[38,128],"paper":[39],"a":[40,67,82,86,106,115],"paradigm":[41],"shift":[42],"current":[45],"trend":[46],"presented":[48],"that":[49,63],"integrates":[50],"layout":[51,121,159],"(with":[54],"full":[55],"parasitics)":[56],"in":[57],"through":[59],"polynomial":[60,108],"metamodels":[61],"such":[62],"system-level":[64],"mixed-signal":[68],"circuit/system":[69],"realistic":[71],"and":[72,93,142,148,164],"accurate":[74,160],"true":[77],"parasitic":[78,123],"netlist":[79],"simulation.":[80],"As":[81],"specific":[83],"case":[84],"study,":[85],"voltage-controlled":[87],"oscillator":[88],"(VCO)":[89],"model":[92,130],"flow":[95],"are":[96,146],"proposed":[97],"assist":[99],"PLL":[101,111],"exploration.":[103,167],"Based":[104],"on":[105],"quadratic":[107],"metamodel,":[109],"achieves":[113],"approximately":[114],"10X":[116],"speedup":[117],"compared":[118],"extracted,":[122],"netlist.":[124],"The":[125,134],"simulations":[126],"using":[127],"attain":[131],"high":[132],"accuracy.":[133],"observed":[135],"error":[136],"for":[137],"simulated":[139],"lock":[140],"time":[141],"average":[143],"power":[144],"consumption":[145],"0.7%":[147],"3%,":[149],"respectively.":[150],"This":[151],"metamodel":[153],"approach":[154],"bridges":[155],"gap":[157],"between":[158],"but":[161],"space":[166]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}