{"id":"https://openalex.org/W2132626852","doi":"https://doi.org/10.1145/2206781.2206855","title":"Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage","display_name":"Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage","publication_year":2012,"publication_date":"2012-05-03","ids":{"openalex":"https://openalex.org/W2132626852","doi":"https://doi.org/10.1145/2206781.2206855","mag":"2132626852"},"language":"en","primary_location":{"id":"doi:10.1145/2206781.2206855","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2206781.2206855","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022752998","display_name":"Marzieh Morshedzadeh Morshedzadeh","orcid":null},"institutions":[{"id":"https://openalex.org/I48379061","display_name":"Shahid Beheshti University","ror":"https://ror.org/0091vmj44","country_code":"IR","type":"education","lineage":["https://openalex.org/I48379061"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Marzieh Morshedzadeh Morshedzadeh","raw_affiliation_strings":["Shahid Beheshti University, G. C., Tehran, Iran","[Shahid Beheshti University G.C., Tehran, Iran]"],"affiliations":[{"raw_affiliation_string":"Shahid Beheshti University, G. C., Tehran, Iran","institution_ids":["https://openalex.org/I48379061"]},{"raw_affiliation_string":"[Shahid Beheshti University G.C., Tehran, Iran]","institution_ids":["https://openalex.org/I48379061"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006710857","display_name":"Ali Jahanian","orcid":"https://orcid.org/0000-0003-2292-4135"},"institutions":[{"id":"https://openalex.org/I48379061","display_name":"Shahid Beheshti University","ror":"https://ror.org/0091vmj44","country_code":"IR","type":"education","lineage":["https://openalex.org/I48379061"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Ali Jahanian","raw_affiliation_strings":["Shahid Beheshti University, G. C., Tehran, Iran","[Shahid Beheshti University G.C., Tehran, Iran]"],"affiliations":[{"raw_affiliation_string":"Shahid Beheshti University, G. C., Tehran, Iran","institution_ids":["https://openalex.org/I48379061"]},{"raw_affiliation_string":"[Shahid Beheshti University G.C., Tehran, Iran]","institution_ids":["https://openalex.org/I48379061"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5022752998"],"corresponding_institution_ids":["https://openalex.org/I48379061"],"apc_list":null,"apc_paid":null,"fwci":0.2455,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.62148552,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"303","last_page":"306"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.7626117467880249},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.7288427352905273},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7273831367492676},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.652981698513031},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6309008002281189},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.603548526763916},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4520646035671234},{"id":"https://openalex.org/keywords/through-silicon-via","display_name":"Through-silicon via","score":0.4118986427783966},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33767199516296387},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.2684336006641388},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.10773661732673645},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09410727024078369},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.06462535262107849}],"concepts":[{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.7626117467880249},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.7288427352905273},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7273831367492676},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.652981698513031},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6309008002281189},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.603548526763916},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4520646035671234},{"id":"https://openalex.org/C45632049","wikidata":"https://www.wikidata.org/wiki/Q1578120","display_name":"Through-silicon via","level":3,"score":0.4118986427783966},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33767199516296387},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.2684336006641388},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.10773661732673645},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09410727024078369},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.06462535262107849},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2206781.2206855","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2206781.2206855","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2045617353","https://openalex.org/W2095841863","https://openalex.org/W2101288449","https://openalex.org/W2116352071","https://openalex.org/W2120970098","https://openalex.org/W2132668926"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W2316202402","https://openalex.org/W2082487009","https://openalex.org/W2258948885","https://openalex.org/W3146360095","https://openalex.org/W2184011203"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"propose":[4],"a":[5,20],"multiplexed":[6],"3D-switch":[7],"box":[8],"architecture":[9,33],"that":[10,30],"decreases":[11],"the":[12,31,35],"number":[13,36],"of":[14,37,45],"TSVs":[15,39],"required":[16],"for":[17],"routing":[18,38],"with":[19],"slight":[21],"overhead":[22],"in":[23,43],"total":[24],"wirelength.":[25],"Our":[26],"experimental":[27],"results":[28],"show":[29],"presented":[32],"reduces":[34],"by":[40],"about":[41],"48%":[42],"cost":[44],"less":[46],"than":[47],"2%":[48],"wirelength":[49],"overhead.":[50]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}