{"id":"https://openalex.org/W2109897403","doi":"https://doi.org/10.1145/2206781.2206802","title":"Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis","display_name":"Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis","publication_year":2012,"publication_date":"2012-05-03","ids":{"openalex":"https://openalex.org/W2109897403","doi":"https://doi.org/10.1145/2206781.2206802","mag":"2109897403"},"language":"en","primary_location":{"id":"doi:10.1145/2206781.2206802","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2206781.2206802","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102119602","display_name":"Keisuke Inoue","orcid":null},"institutions":[{"id":"https://openalex.org/I177738480","display_name":"Japan Advanced Institute of Science and Technology","ror":"https://ror.org/03frj4r98","country_code":"JP","type":"education","lineage":["https://openalex.org/I177738480"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Keisuke Inoue","raw_affiliation_strings":["Japan Advanced Institute of Science and Technology, Ishikawa, Japan"],"affiliations":[{"raw_affiliation_string":"Japan Advanced Institute of Science and Technology, Ishikawa, Japan","institution_ids":["https://openalex.org/I177738480"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112420841","display_name":"Mineo Kaneko","orcid":null},"institutions":[{"id":"https://openalex.org/I177738480","display_name":"Japan Advanced Institute of Science and Technology","ror":"https://ror.org/03frj4r98","country_code":"JP","type":"education","lineage":["https://openalex.org/I177738480"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Mineo Kaneko","raw_affiliation_strings":["Japan Advanced Institute of Science and Technology, Ishikawa, Japan"],"affiliations":[{"raw_affiliation_string":"Japan Advanced Institute of Science and Technology, Ishikawa, Japan","institution_ids":["https://openalex.org/I177738480"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5102119602"],"corresponding_institution_ids":["https://openalex.org/I177738480"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15692337,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"79","last_page":"82"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9069787263870239},{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.7771643400192261},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7170379757881165},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6469097137451172},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5794141292572021},{"id":"https://openalex.org/keywords/resource","display_name":"Resource (disambiguation)","score":0.5334954857826233},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5106547474861145},{"id":"https://openalex.org/keywords/selection","display_name":"Selection (genetic algorithm)","score":0.45525655150413513},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4186279773712158},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.41816359758377075},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.4152514934539795},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4102938175201416},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3744269609451294},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.25296318531036377},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.19140854477882385},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1745913326740265},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.13795578479766846},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.12812671065330505},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10170760750770569},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.0872575044631958},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07954204082489014}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9069787263870239},{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.7771643400192261},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7170379757881165},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6469097137451172},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5794141292572021},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.5334954857826233},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5106547474861145},{"id":"https://openalex.org/C81917197","wikidata":"https://www.wikidata.org/wiki/Q628760","display_name":"Selection (genetic algorithm)","level":2,"score":0.45525655150413513},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4186279773712158},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.41816359758377075},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.4152514934539795},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4102938175201416},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3744269609451294},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.25296318531036377},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.19140854477882385},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1745913326740265},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.13795578479766846},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.12812671065330505},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10170760750770569},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0872575044631958},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07954204082489014},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2206781.2206802","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2206781.2206802","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"id":"https://metadata.un.org/sdg/8","display_name":"Decent work and economic growth"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2064559570","https://openalex.org/W2089192331","https://openalex.org/W2102504603","https://openalex.org/W2114266730","https://openalex.org/W2129183345","https://openalex.org/W2162238157"],"related_works":["https://openalex.org/W2184321560","https://openalex.org/W2166021916","https://openalex.org/W1903431847","https://openalex.org/W1994884893","https://openalex.org/W1839177134","https://openalex.org/W2004001588","https://openalex.org/W2135482679","https://openalex.org/W2084005807","https://openalex.org/W2137686989","https://openalex.org/W2375695813"],"abstract_inverted_index":{"Flip-flop":[0],"(FF)/latch-based":[1],"design":[2,15,22,44,75,102],"has":[3,97],"advantages":[4],"on":[5],"such":[6],"as":[7,66],"area":[8],"and":[9,52,63,81],"power":[10],"compared":[11],"to":[12,55,99],"single":[13],"register-type":[14,82],"(only":[16],"FFs":[17],"or":[18],"latches).":[19],"Considering":[20],"FF/latch-based":[21,43,113],"at":[23],"high-level":[24],"synthesis":[25],"is":[26,45,94],"necessary,":[27],"because":[28],"resource":[29,79,88],"binding":[30,80],"process":[31],"significantly":[32],"affects":[33],"the":[34,46,56,59,73,107],"quality":[35],"of":[36,42,58,61],"resulting":[37],"circuits.":[38],"A":[39],"major":[40],"downside":[41],"increase":[47],"in":[48,77],"resources":[49],"(functional":[50],"units":[51],"registers)":[53],"due":[54],"modification":[57],"lifetimes":[60],"operations":[62],"data.":[64],"Therefore,":[65],"a":[67],"first":[68],"step,":[69],"this":[70],"paper":[71],"addresses":[72],"datapath":[74],"problem":[76],"which":[78,96],"selection":[83],"are":[84],"simultaneously":[85],"optimized":[86],"for":[87],"optimization.":[89],"An":[90],"efficient":[91],"comprehensive":[92],"framework":[93],"presented,":[95],"flexibility":[98],"incorporate":[100],"other":[101],"objectives.":[103],"Experiments":[104],"show":[105],"that":[106],"proposed":[108],"approach":[109],"can":[110],"generate":[111],"resource-efficient":[112],"datapaths.":[114]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
