{"id":"https://openalex.org/W2116036874","doi":"https://doi.org/10.1145/2206781.2206801","title":"Top-down-based symmetrical buffered clock routing","display_name":"Top-down-based symmetrical buffered clock routing","publication_year":2012,"publication_date":"2012-05-03","ids":{"openalex":"https://openalex.org/W2116036874","doi":"https://doi.org/10.1145/2206781.2206801","mag":"2116036874"},"language":"en","primary_location":{"id":"doi:10.1145/2206781.2206801","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2206781.2206801","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071940138","display_name":"Jin-Tai Yan","orcid":"https://orcid.org/0000-0002-7614-2545"},"institutions":[{"id":"https://openalex.org/I59460038","display_name":"Chung Hua University","ror":"https://ror.org/01yzz0f51","country_code":"TW","type":"education","lineage":["https://openalex.org/I59460038"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Jin-Tai Yan","raw_affiliation_strings":["Chung Hua University, Hsinchu, Taiwan Roc"],"affiliations":[{"raw_affiliation_string":"Chung Hua University, Hsinchu, Taiwan Roc","institution_ids":["https://openalex.org/I59460038"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043427027","display_name":"Ming-Chien Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I59460038","display_name":"Chung Hua University","ror":"https://ror.org/01yzz0f51","country_code":"TW","type":"education","lineage":["https://openalex.org/I59460038"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ming-Chien Huang","raw_affiliation_strings":["Chung Hua University, Hsinchu, Taiwan Roc"],"affiliations":[{"raw_affiliation_string":"Chung Hua University, Hsinchu, Taiwan Roc","institution_ids":["https://openalex.org/I59460038"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100442721","display_name":"Zhiwei Chen","orcid":"https://orcid.org/0000-0003-0114-1895"},"institutions":[{"id":"https://openalex.org/I59460038","display_name":"Chung Hua University","ror":"https://ror.org/01yzz0f51","country_code":"TW","type":"education","lineage":["https://openalex.org/I59460038"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Zhi-Wei Chen","raw_affiliation_strings":["Chung Hua University, Hsinchu, Taiwan Roc"],"affiliations":[{"raw_affiliation_string":"Chung Hua University, Hsinchu, Taiwan Roc","institution_ids":["https://openalex.org/I59460038"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5071940138"],"corresponding_institution_ids":["https://openalex.org/I59460038"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.15935919,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"75","last_page":"78"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.8417075872421265},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.7173370122909546},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.6759465932846069},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.6379537582397461},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6339497566223145},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6291984915733337},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.6220477819442749},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.528276264667511},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.4945392310619354},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.45648878812789917},{"id":"https://openalex.org/keywords/vector-clock","display_name":"Vector clock","score":0.42712974548339844},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.4117394983768463},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39902880787849426},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3398081660270691},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21755415201187134},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.196766197681427},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.08169868588447571},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06223258376121521}],"concepts":[{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.8417075872421265},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.7173370122909546},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6759465932846069},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.6379537582397461},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6339497566223145},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6291984915733337},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.6220477819442749},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.528276264667511},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.4945392310619354},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.45648878812789917},{"id":"https://openalex.org/C52563298","wikidata":"https://www.wikidata.org/wiki/Q1413349","display_name":"Vector clock","level":5,"score":0.42712974548339844},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.4117394983768463},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39902880787849426},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3398081660270691},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21755415201187134},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.196766197681427},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.08169868588447571},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06223258376121521}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2206781.2206801","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2206781.2206801","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1507707340","https://openalex.org/W1974610062","https://openalex.org/W2004375829","https://openalex.org/W2023981464","https://openalex.org/W2068670364","https://openalex.org/W2117616504","https://openalex.org/W2122533670","https://openalex.org/W2122944491","https://openalex.org/W2140367260","https://openalex.org/W2148609278","https://openalex.org/W2151933980","https://openalex.org/W2614475470","https://openalex.org/W6630243770","https://openalex.org/W6667666121","https://openalex.org/W6678315013","https://openalex.org/W6682174997"],"related_works":["https://openalex.org/W4247180033","https://openalex.org/W2040807843","https://openalex.org/W4249038728","https://openalex.org/W4231008241","https://openalex.org/W2125201667","https://openalex.org/W2163637408","https://openalex.org/W2617666058","https://openalex.org/W2520965597","https://openalex.org/W1999924508","https://openalex.org/W1938797020"],"abstract_inverted_index":{"It":[0],"is":[1,31],"important":[2],"for":[3,91],"a":[4,13,36,46,81],"synchronous":[5],"design":[6],"to":[7,34,74],"minimize":[8],"the":[9,21,59,88,99],"clock":[10,14,39,43,53,78,84],"skew":[11,44,79],"in":[12,24,80,94],"tree.":[15],"In":[16],"this":[17],"paper,":[18],"based":[19],"on":[20,98],"length-matching":[22],"benefit":[23],"exact":[25],"routing,":[26,54],"an":[27],"efficient":[28],"four-stage":[29],"algorithm":[30],"further":[32],"proposed":[33,65],"generate":[35],"symmetrical":[37,51,82],"buffered":[38,52,83],"tree":[40,85],"with":[41,56,86],"smaller":[42],"under":[45],"given":[47],"slew-rate":[48,89],"constraint.":[49],"For":[50],"compared":[55],"Shih's":[57],"approach,":[58],"experimental":[60],"results":[61],"show":[62],"that":[63],"our":[64],"approach":[66],"can":[67],"use":[68],"extra":[69],"2.54%":[70],"of":[71,77],"total":[72],"resource":[73],"reduce":[75],"85.78%":[76],"satisfying":[87],"constraint":[90],"tested":[92],"benchmarks":[93],"less":[95],"CPU":[96],"time":[97],"average.":[100]},"counts_by_year":[{"year":2017,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
