{"id":"https://openalex.org/W2167314413","doi":"https://doi.org/10.1145/2162131.2162134","title":"Heterogeneous integration to simplify many-core architecture simulations","display_name":"Heterogeneous integration to simplify many-core architecture simulations","publication_year":2012,"publication_date":"2012-01-23","ids":{"openalex":"https://openalex.org/W2167314413","doi":"https://doi.org/10.1145/2162131.2162134","mag":"2167314413"},"language":"en","primary_location":{"id":"doi:10.1145/2162131.2162134","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2162131.2162134","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007097526","display_name":"Rapha\u00ebl Poss","orcid":"https://orcid.org/0000-0001-7067-3145"},"institutions":[{"id":"https://openalex.org/I887064364","display_name":"University of Amsterdam","ror":"https://ror.org/04dkp9463","country_code":"NL","type":"education","lineage":["https://openalex.org/I887064364"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"Raphael Poss","raw_affiliation_strings":["University of Amsterdam, The Netherlands"],"affiliations":[{"raw_affiliation_string":"University of Amsterdam, The Netherlands","institution_ids":["https://openalex.org/I887064364"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047939440","display_name":"Mike Lankamp","orcid":null},"institutions":[{"id":"https://openalex.org/I887064364","display_name":"University of Amsterdam","ror":"https://ror.org/04dkp9463","country_code":"NL","type":"education","lineage":["https://openalex.org/I887064364"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Mike Lankamp","raw_affiliation_strings":["University of Amsterdam, The Netherlands"],"affiliations":[{"raw_affiliation_string":"University of Amsterdam, The Netherlands","institution_ids":["https://openalex.org/I887064364"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047672519","display_name":"M. Irfan Uddin","orcid":"https://orcid.org/0000-0002-1355-3881"},"institutions":[{"id":"https://openalex.org/I887064364","display_name":"University of Amsterdam","ror":"https://ror.org/04dkp9463","country_code":"NL","type":"education","lineage":["https://openalex.org/I887064364"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"M. Irfan Uddin","raw_affiliation_strings":["University of Amsterdam, The Netherlands"],"affiliations":[{"raw_affiliation_string":"University of Amsterdam, The Netherlands","institution_ids":["https://openalex.org/I887064364"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113480678","display_name":"Jaroslav S\u00fdkora","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119419","display_name":"Czech Academy of Sciences, Institute of Information Theory and Automation","ror":"https://ror.org/03h1hsz49","country_code":"CZ","type":"facility","lineage":["https://openalex.org/I202391551","https://openalex.org/I4210119419"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Jaroslav S\u00fdkora","raw_affiliation_strings":["Institute of Information Theory and Automation, Czech Republic"],"affiliations":[{"raw_affiliation_string":"Institute of Information Theory and Automation, Czech Republic","institution_ids":["https://openalex.org/I4210119419"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057958792","display_name":"Leo\u0161 Kafka","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119419","display_name":"Czech Academy of Sciences, Institute of Information Theory and Automation","ror":"https://ror.org/03h1hsz49","country_code":"CZ","type":"facility","lineage":["https://openalex.org/I202391551","https://openalex.org/I4210119419"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Leo\u0161 Kafka","raw_affiliation_strings":["Institute of Information Theory and Automation, Czech Republic"],"affiliations":[{"raw_affiliation_string":"Institute of Information Theory and Automation, Czech Republic","institution_ids":["https://openalex.org/I4210119419"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5007097526"],"corresponding_institution_ids":["https://openalex.org/I887064364"],"apc_list":null,"apc_paid":null,"fwci":3.5676,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.93223894,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"17","last_page":"24"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.787947416305542},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.715719997882843},{"id":"https://openalex.org/keywords/concurrency","display_name":"Concurrency","score":0.6857914328575134},{"id":"https://openalex.org/keywords/many-core","display_name":"Many core","score":0.589206337928772},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5728487968444824},{"id":"https://openalex.org/keywords/stack","display_name":"Stack (abstract data type)","score":0.5578234195709229},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5542574524879456},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.5251645445823669},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5002565383911133},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49433016777038574},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.44671815633773804},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3530593514442444},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2865578532218933}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.787947416305542},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.715719997882843},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.6857914328575134},{"id":"https://openalex.org/C3020431745","wikidata":"https://www.wikidata.org/wiki/Q25325220","display_name":"Many core","level":2,"score":0.589206337928772},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5728487968444824},{"id":"https://openalex.org/C9395851","wikidata":"https://www.wikidata.org/wiki/Q177929","display_name":"Stack (abstract data type)","level":2,"score":0.5578234195709229},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5542574524879456},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.5251645445823669},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5002565383911133},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49433016777038574},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.44671815633773804},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3530593514442444},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2865578532218933},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/2162131.2162134","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2162131.2162134","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools","raw_type":"proceedings-article"},{"id":"pmh:oai:dare.uva.nl:openaire_cris_publications/bcb561db-f7b9-4637-b4df-8d25685a8f25","is_oa":false,"landing_page_url":"https://dare.uva.nl/personal/pure/en/publications/heterogeneous-integration-to-simplify-manycore-architecture-simulations(bcb561db-f7b9-4637-b4df-8d25685a8f25).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400088","display_name":"UvA-DARE (University of Amsterdam)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I887064364","host_organization_name":"University of Amsterdam","host_organization_lineage":["https://openalex.org/I887064364"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Poss, R, Lankamp, M, Irfan Uddin, M, Sykora, J & Kafka, L 2012, Heterogeneous integration to simplify many-core architecture simulations. in Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools. New York, NY, pp. 17-24, 4th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO\u201912), 1/01/12. https://doi.org/10.1145/2162131.2162134","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:dare.uva.nl:publications/bcb561db-f7b9-4637-b4df-8d25685a8f25","is_oa":false,"landing_page_url":"https://handle.uba.uva.nl/personal/pure/en/publications/heterogeneous-integration-to-simplify-manycore-architecture-simulations(bcb561db-f7b9-4637-b4df-8d25685a8f25).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400088","display_name":"UvA-DARE (University of Amsterdam)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I887064364","host_organization_name":"University of Amsterdam","host_organization_lineage":["https://openalex.org/I887064364"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Poss, R, Lankamp, M, Irfan Uddin, M, Sykora, J & Kafka, L 2012, Heterogeneous integration to simplify many-core architecture simulations. in Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools. New York, NY, pp. 17-24, 4th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO\u201912), 1/01/12. https://doi.org/10.1145/2162131.2162134","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.47999998927116394}],"awards":[{"id":"https://openalex.org/G7406071558","display_name":null,"funder_award_id":"FP7-ICT-215216","funder_id":"https://openalex.org/F4320334960","funder_display_name":"Seventh Framework Programme"}],"funders":[{"id":"https://openalex.org/F4320334960","display_name":"Seventh Framework Programme","ror":"https://ror.org/00k4n6c32"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1594765359","https://openalex.org/W2002871272","https://openalex.org/W2044206819","https://openalex.org/W2063057674","https://openalex.org/W2066339098","https://openalex.org/W2078652796","https://openalex.org/W2090092300","https://openalex.org/W2100817684","https://openalex.org/W2115753002","https://openalex.org/W2118102322","https://openalex.org/W2119047985","https://openalex.org/W2132855739","https://openalex.org/W2138030026","https://openalex.org/W2150073849","https://openalex.org/W2152530860","https://openalex.org/W2155066383","https://openalex.org/W2157733805","https://openalex.org/W2167809671","https://openalex.org/W2168024542","https://openalex.org/W2168075869","https://openalex.org/W2168497150","https://openalex.org/W2462402886","https://openalex.org/W3010613301","https://openalex.org/W3137094666","https://openalex.org/W6679774868"],"related_works":["https://openalex.org/W4255057712","https://openalex.org/W4251458280","https://openalex.org/W2512412909","https://openalex.org/W1547865754","https://openalex.org/W2126398188","https://openalex.org/W2116570023","https://openalex.org/W4210605172","https://openalex.org/W2127157145","https://openalex.org/W4245707462","https://openalex.org/W4248999141"],"abstract_inverted_index":{"The":[0,24,49],"EU":[1],"Apple-CORE":[2],"project":[3],"has":[4,33],"explored":[5],"the":[6,27,30,43,57],"design":[7],"and":[8,18,39,69,88],"implementation":[9],"of":[10,26,42,59,65],"novel":[11],"general-purpose":[12],"many-core":[13],"chips":[14],"featuring":[15],"hardware":[16,19,67],"microthreading":[17],"support":[20],"for":[21],"concurrency":[22],"management.":[23],"introduction":[25],"latter":[28],"in":[29,52],"cores":[31],"ISA":[32],"required":[34],"simultaneous":[35],"investigation":[36],"into":[37],"compilers":[38],"multiple":[40],"layers":[41],"software":[44,78],"stack,":[45],"including":[46],"operating":[47],"systems.":[48],"main":[50],"challenge":[51],"such":[53],"vertical":[54],"approaches":[55],"is":[56],"cost":[58],"implementing":[60],"simultaneously":[61],"a":[62,70],"detailed":[63],"simulation":[64],"new":[66],"components":[68],"complete":[71],"system":[72],"platform":[73],"suitable":[74],"to":[75,91],"run":[76],"large":[77],"bench-maks.":[79],"In":[80],"this":[81,92],"paper,":[82],"we":[83],"describe":[84],"our":[85,89],"use":[86],"case":[87],"solutions":[90],"challenge.":[93]},"counts_by_year":[{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":1}],"updated_date":"2026-03-25T13:04:00.132906","created_date":"2025-10-10T00:00:00"}
