{"id":"https://openalex.org/W2148797773","doi":"https://doi.org/10.1145/2155620.2155673","title":"Efficiently enabling conventional block sizes for very large die-stacked DRAM caches","display_name":"Efficiently enabling conventional block sizes for very large die-stacked DRAM caches","publication_year":2011,"publication_date":"2011-12-03","ids":{"openalex":"https://openalex.org/W2148797773","doi":"https://doi.org/10.1145/2155620.2155673","mag":"2148797773"},"language":"en","primary_location":{"id":"doi:10.1145/2155620.2155673","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2155620.2155673","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102835155","display_name":"Gabriel H. Loh","orcid":"https://orcid.org/0000-0002-4616-0144"},"institutions":[{"id":"https://openalex.org/I1311921367","display_name":"Advanced Micro Devices (Canada)","ror":"https://ror.org/02yh0k313","country_code":"CA","type":"company","lineage":["https://openalex.org/I1311921367","https://openalex.org/I4210137977"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Gabriel H. Loh","raw_affiliation_strings":["AMD Research, Advanced Micro Devices, Inc"],"affiliations":[{"raw_affiliation_string":"AMD Research, Advanced Micro Devices, Inc","institution_ids":["https://openalex.org/I1311921367"]}]},{"author_position":"last","author":{"id":null,"display_name":"Mark D. Hill","orcid":null},"institutions":[{"id":"https://openalex.org/I4210137977","display_name":"Advanced Micro Devices (United States)","ror":"https://ror.org/04kd6c783","country_code":"US","type":"company","lineage":["https://openalex.org/I4210137977"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark D. Hill","raw_affiliation_strings":["University of Wisconsin, Madison, and AMD Research, Advanced Micro Devices, Inc"],"affiliations":[{"raw_affiliation_string":"University of Wisconsin, Madison, and AMD Research, Advanced Micro Devices, Inc","institution_ids":["https://openalex.org/I4210137977"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5102835155"],"corresponding_institution_ids":["https://openalex.org/I1311921367"],"apc_list":null,"apc_paid":null,"fwci":13.1432,"has_fulltext":false,"cited_by_count":232,"citation_normalized_percentile":{"value":0.99024121,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":95,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"454","last_page":"464"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.9055784940719604},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7411022186279297},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6945019960403442},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.6689121127128601},{"id":"https://openalex.org/keywords/byte","display_name":"Byte","score":0.4973442852497101},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.4833052158355713},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.48257604241371155},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4669156074523926},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.43748974800109863},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4305541515350342},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.42356932163238525},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4154367446899414},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39900022745132446},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.22912395000457764},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.22816425561904907},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.21340146660804749},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.09492179751396179}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.9055784940719604},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7411022186279297},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6945019960403442},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.6689121127128601},{"id":"https://openalex.org/C43364308","wikidata":"https://www.wikidata.org/wiki/Q8799","display_name":"Byte","level":2,"score":0.4973442852497101},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.4833052158355713},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48257604241371155},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4669156074523926},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.43748974800109863},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4305541515350342},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.42356932163238525},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4154367446899414},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39900022745132446},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.22912395000457764},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.22816425561904907},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.21340146660804749},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.09492179751396179},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2155620.2155673","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2155620.2155673","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6899999976158142}],"awards":[{"id":"https://openalex.org/G4490573464","display_name":null,"funder_award_id":"MSN123960/DOE890426","funder_id":"https://openalex.org/F4320338291","funder_display_name":"Sandia National Laboratories"},{"id":"https://openalex.org/G4515486537","display_name":null,"funder_award_id":"CNS-0720565CNS-0916725CNS-1117280","funder_id":"https://openalex.org/F4320337388","funder_display_name":"Division of Computer and Network Systems"},{"id":"https://openalex.org/G7789361240","display_name":null,"funder_award_id":"MSN123960/DOE890426","funder_id":"https://openalex.org/F4320306084","funder_display_name":"U.S. Department of Energy"}],"funders":[{"id":"https://openalex.org/F4320306084","display_name":"U.S. Department of Energy","ror":"https://ror.org/01bj3aw27"},{"id":"https://openalex.org/F4320337388","display_name":"Division of Computer and Network Systems","ror":"https://ror.org/02rdzmk74"},{"id":"https://openalex.org/F4320338291","display_name":"Sandia National Laboratories","ror":"https://ror.org/01apwpt12"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":37,"referenced_works":["https://openalex.org/W1666750238","https://openalex.org/W1984271364","https://openalex.org/W1987131925","https://openalex.org/W1993089791","https://openalex.org/W2008494287","https://openalex.org/W2038932419","https://openalex.org/W2044206819","https://openalex.org/W2046996113","https://openalex.org/W2047043979","https://openalex.org/W2071208935","https://openalex.org/W2074113453","https://openalex.org/W2092406519","https://openalex.org/W2099372413","https://openalex.org/W2099815586","https://openalex.org/W2101791918","https://openalex.org/W2109292926","https://openalex.org/W2114139104","https://openalex.org/W2114542420","https://openalex.org/W2115172404","https://openalex.org/W2117816012","https://openalex.org/W2122473394","https://openalex.org/W2122636510","https://openalex.org/W2128317922","https://openalex.org/W2131413854","https://openalex.org/W2141736089","https://openalex.org/W2143807959","https://openalex.org/W2145547293","https://openalex.org/W2148103955","https://openalex.org/W2153378664","https://openalex.org/W2157860533","https://openalex.org/W2164264749","https://openalex.org/W2168514350","https://openalex.org/W2171148960","https://openalex.org/W2985278913","https://openalex.org/W3139689176","https://openalex.org/W4232664043","https://openalex.org/W4233276666"],"related_works":["https://openalex.org/W2516517078","https://openalex.org/W1992487929","https://openalex.org/W4386903460","https://openalex.org/W4293430534","https://openalex.org/W4297812927","https://openalex.org/W2335743642","https://openalex.org/W2800412005","https://openalex.org/W2154976966","https://openalex.org/W2536264121","https://openalex.org/W4382618825"],"abstract_inverted_index":{"Die-stacking":[0],"technology":[1],"enables":[2],"multiple":[3],"layers":[4],"of":[5,16,31,50],"DRAM":[6,18,43,67,72],"to":[7,28,88],"be":[8,29],"integrated":[9],"with":[10,45],"multicore":[11],"processors.":[12],"A":[13],"promising":[14],"use":[15],"stacked":[17],"is":[19,26,57,68],"as":[20],"a":[21,41],"cache,":[22],"since":[23],"its":[24],"capacity":[25],"insufficient":[27],"all":[30,35],"main":[32],"memory":[33],"(for":[34],"but":[36,84],"some":[37],"embedded":[38],"systems).":[39],"However,":[40],"1GB":[42],"cache":[44],"64-byte":[46],"blocks":[47,79],"requires":[48],"96MB":[49],"tag":[51,75],"storage.":[52],"Placing":[53],"these":[54],"tags":[55],"on-chip":[56,61],"impractical":[58],"(larger":[59],"than":[60],"L3s)":[62],"while":[63],"putting":[64],"them":[65],"in":[66],"slow":[69],"(two":[70],"full":[71],"accesses":[73],"for":[74],"and":[76,80],"data).":[77],"Larger":[78],"sub-blocking":[81],"are":[82],"possible,":[83],"less":[85],"robust":[86],"due":[87],"fragmentation.":[89]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":11},{"year":2021,"cited_by_count":6},{"year":2020,"cited_by_count":15},{"year":2019,"cited_by_count":13},{"year":2018,"cited_by_count":36},{"year":2017,"cited_by_count":30},{"year":2016,"cited_by_count":34},{"year":2015,"cited_by_count":26},{"year":2014,"cited_by_count":18},{"year":2013,"cited_by_count":21},{"year":2012,"cited_by_count":12}],"updated_date":"2026-04-16T08:26:57.006410","created_date":"2025-10-10T00:00:00"}