{"id":"https://openalex.org/W2095258606","doi":"https://doi.org/10.1145/2155620.2155671","title":"SHiP","display_name":"SHiP","publication_year":2011,"publication_date":"2011-12-03","ids":{"openalex":"https://openalex.org/W2095258606","doi":"https://doi.org/10.1145/2155620.2155671","mag":"2095258606"},"language":"en","primary_location":{"id":"doi:10.1145/2155620.2155671","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2155620.2155671","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028220093","display_name":"Carole-Jean Wu","orcid":"https://orcid.org/0000-0002-9032-7239"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Carole-Jean Wu","raw_affiliation_strings":["Princeton University, Princeton, NJ"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Princeton University, Princeton, NJ","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078825915","display_name":"Aamer Jaleel","orcid":"https://orcid.org/0000-0002-5709-2992"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Aamer Jaleel","raw_affiliation_strings":["Intel Corporation, VSSAD, Hudson, MA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, VSSAD, Hudson, MA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083700422","display_name":"Will Hasenplaugh","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Will Hasenplaugh","raw_affiliation_strings":["Intel Corporation, VSSAD, Hudson, MA, and Massachusetts Institute of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, VSSAD, Hudson, MA, and Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I63966007"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002015508","display_name":"Margaret Martonosi","orcid":"https://orcid.org/0000-0001-9683-8032"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Margaret Martonosi","raw_affiliation_strings":["Princeton University, Princeton, NJ"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Princeton University, Princeton, NJ","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048387429","display_name":"Simon C. Steely","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Simon C. Steely","raw_affiliation_strings":["Intel Corporation, VSSAD, Hudson, MA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, VSSAD, Hudson, MA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024384625","display_name":"Joel Emer","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joel Emer","raw_affiliation_strings":["Intel Corporation, VSSAD, Hudson, MA, and Massachusetts Institute of Technology, Cambridge, MA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, VSSAD, Hudson, MA, and Massachusetts Institute of Technology, Cambridge, MA","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I63966007"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":242,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"430","last_page":"441"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.848241925239563},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.8013278245925903},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.6079939007759094},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.6022434234619141},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.5869698524475098},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5431020855903625},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.5130957365036011},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4618169069290161},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.4553329348564148},{"id":"https://openalex.org/keywords/bus-sniffing","display_name":"Bus sniffing","score":0.4438457190990448},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4282084107398987},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3765772581100464},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.36791497468948364},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.26130038499832153}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.848241925239563},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.8013278245925903},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.6079939007759094},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.6022434234619141},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.5869698524475098},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5431020855903625},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.5130957365036011},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4618169069290161},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.4553329348564148},{"id":"https://openalex.org/C51185590","wikidata":"https://www.wikidata.org/wiki/Q1017228","display_name":"Bus sniffing","level":5,"score":0.4438457190990448},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4282084107398987},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3765772581100464},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.36791497468948364},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.26130038499832153}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2155620.2155671","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2155620.2155671","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7200000286102295,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G1173409761","display_name":null,"funder_award_id":"CNS-0509402CNS-0720561","funder_id":"https://openalex.org/F4320337388","funder_display_name":"Division of Computer and Network Systems"}],"funders":[{"id":"https://openalex.org/F4320337388","display_name":"Division of Computer and Network Systems","ror":"https://ror.org/02rdzmk74"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W1578858535","https://openalex.org/W1860107648","https://openalex.org/W1968029317","https://openalex.org/W1968271929","https://openalex.org/W1987225815","https://openalex.org/W1999621870","https://openalex.org/W2029577083","https://openalex.org/W2072853307","https://openalex.org/W2074303271","https://openalex.org/W2100901045","https://openalex.org/W2109292926","https://openalex.org/W2110999128","https://openalex.org/W2120629815","https://openalex.org/W2122108187","https://openalex.org/W2124350608","https://openalex.org/W2125328729","https://openalex.org/W2128060503","https://openalex.org/W2131806537","https://openalex.org/W2134633067","https://openalex.org/W2135089498","https://openalex.org/W2140906558","https://openalex.org/W2143443573","https://openalex.org/W2149172130","https://openalex.org/W2150196852","https://openalex.org/W2152356827","https://openalex.org/W2157800896","https://openalex.org/W2160996172","https://openalex.org/W2164813972","https://openalex.org/W2166620913","https://openalex.org/W2301831060","https://openalex.org/W3158149042","https://openalex.org/W4239813889","https://openalex.org/W6634647146"],"related_works":["https://openalex.org/W2161101294","https://openalex.org/W2148571123","https://openalex.org/W2026179701","https://openalex.org/W4380881125","https://openalex.org/W2184371594","https://openalex.org/W4312759433","https://openalex.org/W2302406141","https://openalex.org/W2034465099","https://openalex.org/W2113875634","https://openalex.org/W2365803410"],"abstract_inverted_index":{"The":[0],"shared":[1],"last-level":[2],"caches":[3],"in":[4,10],"CMPs":[5],"play":[6],"an":[7,60],"important":[8],"role":[9],"improving":[11],"application":[12],"performance":[13],"and":[14,39],"reducing":[15],"off-chip":[16],"memory":[17],"bandwidth":[18],"requirements.":[19],"In":[20],"order":[21],"to":[22,53],"use":[23],"LLCs":[24],"more":[25],"efficiently,":[26],"recent":[27],"research":[28],"has":[29],"shown":[30],"that":[31],"changing":[32],"the":[33,56],"re-reference":[34,57],"prediction":[35],"on":[36],"cache":[37,40,45,62],"insertions":[38],"hits":[41],"can":[42],"significantly":[43],"improve":[44],"performance.":[46],"A":[47],"fundamental":[48],"challenge,":[49],"however,":[50],"is":[51],"how":[52],"best":[54],"predict":[55],"pattern":[58],"of":[59],"incoming":[61],"line.":[63]},"counts_by_year":[{"year":2026,"cited_by_count":5},{"year":2025,"cited_by_count":13},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":11},{"year":2022,"cited_by_count":13},{"year":2021,"cited_by_count":23},{"year":2020,"cited_by_count":12},{"year":2019,"cited_by_count":19},{"year":2018,"cited_by_count":16},{"year":2017,"cited_by_count":23},{"year":2016,"cited_by_count":27},{"year":2015,"cited_by_count":30},{"year":2014,"cited_by_count":13},{"year":2013,"cited_by_count":20},{"year":2012,"cited_by_count":10}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2016-06-24T00:00:00"}