{"id":"https://openalex.org/W2142875853","doi":"https://doi.org/10.1145/2155620.2155664","title":"Reducing memory interference in multicore systems via application-aware memory channel partitioning","display_name":"Reducing memory interference in multicore systems via application-aware memory channel partitioning","publication_year":2011,"publication_date":"2011-12-03","ids":{"openalex":"https://openalex.org/W2142875853","doi":"https://doi.org/10.1145/2155620.2155664","mag":"2142875853"},"language":"en","primary_location":{"id":"doi:10.1145/2155620.2155664","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2155620.2155664","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090568028","display_name":"Sai Prashanth Muralidhara","orcid":null},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Sai Prashanth Muralidhara","raw_affiliation_strings":["Pennsylvania State University"],"affiliations":[{"raw_affiliation_string":"Pennsylvania State University","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013984674","display_name":"Lavanya Subramanian","orcid":"https://orcid.org/0000-0001-9809-3361"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lavanya Subramanian","raw_affiliation_strings":["Carnegie Mellon University","Carnegie Mellon Univ (USA)"],"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Carnegie Mellon Univ (USA)","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050695684","display_name":"Onur Mutlu","orcid":"https://orcid.org/0000-0002-0075-2312"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Onur Mutlu","raw_affiliation_strings":["Carnegie Mellon University","Carnegie Mellon Univ (USA)"],"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Carnegie Mellon Univ (USA)","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007116603","display_name":"Mahmut Kandemir","orcid":"https://orcid.org/0000-0002-9940-9951"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mahmut Kandemir","raw_affiliation_strings":["Pennsylvania State University"],"affiliations":[{"raw_affiliation_string":"Pennsylvania State University","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041937385","display_name":"Thomas Moscibroda","orcid":"https://orcid.org/0000-0002-8729-7841"},"institutions":[{"id":"https://openalex.org/I4210113369","display_name":"Microsoft Research Asia (China)","ror":"https://ror.org/0300m5276","country_code":"CN","type":"company","lineage":["https://openalex.org/I1290206253","https://openalex.org/I4210113369"]},{"id":"https://openalex.org/I1290206253","display_name":"Microsoft (United States)","ror":"https://ror.org/00d0nc645","country_code":"US","type":"company","lineage":["https://openalex.org/I1290206253"]}],"countries":["CN","US"],"is_corresponding":false,"raw_author_name":"Thomas Moscibroda","raw_affiliation_strings":["Microsoft Research Asia","[Microsoft Research Asia, USA]"],"affiliations":[{"raw_affiliation_string":"Microsoft Research Asia","institution_ids":["https://openalex.org/I4210113369"]},{"raw_affiliation_string":"[Microsoft Research Asia, USA]","institution_ids":["https://openalex.org/I1290206253"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5090568028"],"corresponding_institution_ids":["https://openalex.org/I130769515"],"apc_list":null,"apc_paid":null,"fwci":18.2957,"has_fulltext":false,"cited_by_count":274,"citation_normalized_percentile":{"value":0.99447565,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"374","last_page":"385"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8054704070091248},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.6289299130439758},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5803090929985046},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.5711453557014465},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.5393445491790771},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.5351966619491577},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.5207931399345398},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5160012245178223},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5065392255783081},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.47869423031806946},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.4611279368400574},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44243982434272766},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.4228630065917969},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.38281741738319397},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3820500373840332},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.24941584467887878},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2450292706489563},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.21444132924079895},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0899043083190918}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8054704070091248},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.6289299130439758},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5803090929985046},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.5711453557014465},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.5393445491790771},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.5351966619491577},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.5207931399345398},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5160012245178223},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5065392255783081},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.47869423031806946},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.4611279368400574},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44243982434272766},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.4228630065917969},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.38281741738319397},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3820500373840332},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.24941584467887878},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2450292706489563},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.21444132924079895},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0899043083190918},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":6,"locations":[{"id":"doi:10.1145/2155620.2155664","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2155620.2155664","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.207.8497","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.207.8497","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.cmu.edu/%7Esafari/tr/tr-2011-002.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.220.6810","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.220.6810","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.pdl.cmu.edu/PDL-FTP/associated/memory-channel-partitioning-micro11.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.221.7263","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.221.7263","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.research.microsoft.com/en-us/um/people/moscitho/Publications/MICRO_2011.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.297.2285","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.297.2285","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://users.ece.cmu.edu/~omutlu/pub/memory-channel-partitioning-TR-SAFARI-2011-002.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.642.4989","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.642.4989","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.cmu.edu/~ece447/s13/lib/exe/fetch.php?media=muralidhara_et_al._-_2011_-_reducing_memory_interference_in_multicore_systems_via_application-aware_memory_channel_partitioning.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2173383247","display_name":null,"funder_award_id":"CAREER Award CCF-095324611473971147388115247910178820963839","funder_id":"https://openalex.org/F4320337387","funder_display_name":"Division of Computing and Communication Foundations"}],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"},{"id":"https://openalex.org/F4320307764","display_name":"Microsoft","ror":"https://ror.org/00d0nc645"},{"id":"https://openalex.org/F4320337387","display_name":"Division of Computing and Communication Foundations","ror":"https://ror.org/01mng8331"},{"id":"https://openalex.org/F4320338281","display_name":"Army Research Office","ror":"https://ror.org/05epdh915"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W1504046403","https://openalex.org/W1579491185","https://openalex.org/W1964316448","https://openalex.org/W1980927950","https://openalex.org/W2025304002","https://openalex.org/W2098040113","https://openalex.org/W2098278566","https://openalex.org/W2100384468","https://openalex.org/W2102871765","https://openalex.org/W2103397328","https://openalex.org/W2106342588","https://openalex.org/W2107333973","https://openalex.org/W2115172404","https://openalex.org/W2119473230","https://openalex.org/W2121256363","https://openalex.org/W2123306627","https://openalex.org/W2129573249","https://openalex.org/W2134633067","https://openalex.org/W2135675903","https://openalex.org/W2140455011","https://openalex.org/W2143823686","https://openalex.org/W2144154231","https://openalex.org/W2145451976","https://openalex.org/W2145988169","https://openalex.org/W2149897852","https://openalex.org/W2159908132","https://openalex.org/W2162838417","https://openalex.org/W2166874382","https://openalex.org/W2182315535","https://openalex.org/W3152438252","https://openalex.org/W4210790398","https://openalex.org/W4236010665","https://openalex.org/W4236312724","https://openalex.org/W4236382111","https://openalex.org/W4238816702","https://openalex.org/W4239813889","https://openalex.org/W4240262711","https://openalex.org/W4247787189","https://openalex.org/W6677612816"],"related_works":["https://openalex.org/W2155373950","https://openalex.org/W2145210935","https://openalex.org/W2138825797","https://openalex.org/W4243618206","https://openalex.org/W2587873888","https://openalex.org/W3108993429","https://openalex.org/W2782503170","https://openalex.org/W2041174925","https://openalex.org/W2047684617","https://openalex.org/W4233816696"],"abstract_inverted_index":{"Main":[0],"memory":[1,19,48,53],"is":[2,21],"a":[3,10,58],"major":[4],"shared":[5],"resource":[6],"among":[7],"cores":[8],"in":[9,46,57],"multicore":[11],"system.":[12],"If":[13],"the":[14,35,43,47],"interference":[15,38],"between":[16,39],"different":[17],"applications'":[18],"requests":[20,54],"not":[22],"controlled":[23],"effectively,":[24],"system":[25,62],"performance":[26],"can":[27],"degrade":[28],"significantly.":[29],"Previous":[30],"work":[31],"aimed":[32],"to":[33],"mitigate":[34],"problem":[36],"of":[37],"applications":[40,56],"by":[41,51],"changing":[42],"scheduling":[44],"policy":[45],"controller,":[49],"i.e.,":[50],"prioritizing":[52],"from":[55],"way":[59],"that":[60],"benefits":[61],"performance.":[63]},"counts_by_year":[{"year":2025,"cited_by_count":6},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":8},{"year":2021,"cited_by_count":9},{"year":2020,"cited_by_count":16},{"year":2019,"cited_by_count":20},{"year":2018,"cited_by_count":27},{"year":2017,"cited_by_count":32},{"year":2016,"cited_by_count":45},{"year":2015,"cited_by_count":32},{"year":2014,"cited_by_count":30},{"year":2013,"cited_by_count":27},{"year":2012,"cited_by_count":13}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
