{"id":"https://openalex.org/W2114800225","doi":"https://doi.org/10.1145/2155620.2155646","title":"CoreRacer","display_name":"CoreRacer","publication_year":2011,"publication_date":"2011-12-03","ids":{"openalex":"https://openalex.org/W2114800225","doi":"https://doi.org/10.1145/2155620.2155646","mag":"2114800225"},"language":"en","primary_location":{"id":"doi:10.1145/2155620.2155646","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2155620.2155646","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071035949","display_name":"Gilles Pokam","orcid":"https://orcid.org/0009-0002-4363-5383"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":true,"raw_author_name":"Gilles Pokam","raw_affiliation_strings":["Intel Corporation","Intel Corp., USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]},{"raw_affiliation_string":"Intel Corp., USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102155812","display_name":"Cristiano Pereira","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Cristiano Pereira","raw_affiliation_strings":["Intel Corporation","Intel Corp., USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]},{"raw_affiliation_string":"Intel Corp., USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109635991","display_name":"Shiliang Hu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Shiliang Hu","raw_affiliation_strings":["Intel Corporation","Intel Corp., USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]},{"raw_affiliation_string":"Intel Corp., USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007158460","display_name":"Ali-Reza Adl-Tabatabai","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Ali-Reza Adl-Tabatabai","raw_affiliation_strings":["Intel Corporation","Intel Corp., USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]},{"raw_affiliation_string":"Intel Corp., USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005286439","display_name":"Justin Gottschlich","orcid":"https://orcid.org/0000-0003-2742-9205"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Justin Gottschlich","raw_affiliation_strings":["Intel Corporation","Intel Corp., USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]},{"raw_affiliation_string":"Intel Corp., USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074393185","display_name":"Jung-Woo Ha","orcid":"https://orcid.org/0000-0002-7400-7681"},"institutions":[{"id":"https://openalex.org/I1291425158","display_name":"Google (United States)","ror":"https://ror.org/00njsd438","country_code":"US","type":"company","lineage":["https://openalex.org/I1291425158","https://openalex.org/I4210128969"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jungwoo Ha","raw_affiliation_strings":["Google","Google, USA"],"affiliations":[{"raw_affiliation_string":"Google","institution_ids":["https://openalex.org/I1291425158"]},{"raw_affiliation_string":"Google, USA","institution_ids":["https://openalex.org/I1291425158"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101174906","display_name":"Youfeng Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Youfeng Wu","raw_affiliation_strings":["Intel Corporation","Intel Corp., USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]},{"raw_affiliation_string":"Intel Corp., USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5071035949"],"corresponding_institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"],"apc_list":null,"apc_paid":null,"fwci":5.1354,"has_fulltext":false,"cited_by_count":35,"citation_normalized_percentile":{"value":0.95903149,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"216","last_page":"225"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8777253031730652},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.7477163076400757},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6687450408935547},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.6008259654045105},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.5410853624343872},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4898345172405243},{"id":"https://openalex.org/keywords/distributed-shared-memory","display_name":"Distributed shared memory","score":0.4893791079521179},{"id":"https://openalex.org/keywords/memory-model","display_name":"Memory model","score":0.42228779196739197},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.40830326080322266},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.3567247688770294},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3309892416000366},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.31302857398986816},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2746788263320923},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.16341909766197205},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.11171084642410278},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.093629390001297}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8777253031730652},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.7477163076400757},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6687450408935547},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.6008259654045105},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.5410853624343872},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4898345172405243},{"id":"https://openalex.org/C39528615","wikidata":"https://www.wikidata.org/wiki/Q1229610","display_name":"Distributed shared memory","level":5,"score":0.4893791079521179},{"id":"https://openalex.org/C12186640","wikidata":"https://www.wikidata.org/wiki/Q6815743","display_name":"Memory model","level":3,"score":0.42228779196739197},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.40830326080322266},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.3567247688770294},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3309892416000366},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.31302857398986816},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2746788263320923},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.16341909766197205},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.11171084642410278},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.093629390001297}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2155620.2155646","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2155620.2155646","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6200000047683716,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W8271523","https://openalex.org/W11234669","https://openalex.org/W1510808677","https://openalex.org/W2012431717","https://openalex.org/W2092393083","https://openalex.org/W2095600927","https://openalex.org/W2098370715","https://openalex.org/W2100189461","https://openalex.org/W2105393274","https://openalex.org/W2106471636","https://openalex.org/W2108806129","https://openalex.org/W2114488210","https://openalex.org/W2120261600","https://openalex.org/W2121118021","https://openalex.org/W2127731413","https://openalex.org/W2129663982","https://openalex.org/W2130473288","https://openalex.org/W2141463837","https://openalex.org/W2142892618","https://openalex.org/W2150042079","https://openalex.org/W2152423679","https://openalex.org/W2152795747","https://openalex.org/W2153456949","https://openalex.org/W2154698535","https://openalex.org/W2159324407","https://openalex.org/W2171956059","https://openalex.org/W2313516520","https://openalex.org/W3145483441","https://openalex.org/W3145543123","https://openalex.org/W3147113554","https://openalex.org/W3147275543","https://openalex.org/W4246906397"],"related_works":["https://openalex.org/W1965261831","https://openalex.org/W4291186713","https://openalex.org/W1495085183","https://openalex.org/W2953079396","https://openalex.org/W2145592252","https://openalex.org/W1590714121","https://openalex.org/W2107163823","https://openalex.org/W2089398893","https://openalex.org/W1512842870","https://openalex.org/W2070949616"],"abstract_inverted_index":{"Shared":[0],"memory":[1,15,27,41,74],"multiprocessors":[2],"are":[3,50],"difficult":[4],"to":[5,52],"program":[6],"because":[7,57],"of":[8,38],"the":[9,14,39,60,64],"non-deterministic":[10],"ways":[11],"in":[12],"which":[13],"operations":[16],"from":[17],"different":[18],"threads":[19,44],"interleave.":[20],"To":[21],"address":[22],"this":[23],"issue,":[24],"many":[25],"hardware-based":[26],"race":[28],"recorders":[29],"have":[30],"been":[31],"proposed":[32],"that":[33],"efficiently":[34],"log":[35],"an":[36],"ordering":[37],"shared":[40],"interleavings":[42],"between":[43],"for":[45],"deterministic":[46],"replay.":[47],"These":[48],"approaches":[49],"challenging":[51],"integrate":[53],"into":[54],"current":[55],"processors":[56],"they":[58,68],"change":[59],"cache":[61],"subsystem":[62],"or":[63],"coherence":[65],"protocol,":[66],"and":[67],"mostly":[69],"support":[70],"a":[71],"sequentially":[72],"consistent":[73],"model.":[75]},"counts_by_year":[{"year":2023,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":7},{"year":2013,"cited_by_count":12},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2016-06-24T00:00:00"}
