{"id":"https://openalex.org/W2081996219","doi":"https://doi.org/10.1145/2145694.2145742","title":"Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only)","display_name":"Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only)","publication_year":2012,"publication_date":"2012-02-22","ids":{"openalex":"https://openalex.org/W2081996219","doi":"https://doi.org/10.1145/2145694.2145742","mag":"2081996219"},"language":"en","primary_location":{"id":"doi:10.1145/2145694.2145742","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2145694.2145742","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047566052","display_name":"Fatemeh Sadat Pourhashemi","orcid":null},"institutions":[{"id":"https://openalex.org/I158248296","display_name":"Amirkabir University of Technology","ror":"https://ror.org/04gzbav43","country_code":"IR","type":"education","lineage":["https://openalex.org/I158248296"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Fatemeh Sadat Pourhashemi","raw_affiliation_strings":["Amirkabir University of Technology, Tehran, Iran","Amirkabir University of Technology, Tehran, IRAN"],"affiliations":[{"raw_affiliation_string":"Amirkabir University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I158248296"]},{"raw_affiliation_string":"Amirkabir University of Technology, Tehran, IRAN","institution_ids":["https://openalex.org/I158248296"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075732511","display_name":"Morteza Saheb Zamani","orcid":"https://orcid.org/0000-0002-0826-1091"},"institutions":[{"id":"https://openalex.org/I158248296","display_name":"Amirkabir University of Technology","ror":"https://ror.org/04gzbav43","country_code":"IR","type":"education","lineage":["https://openalex.org/I158248296"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Morteza Saheb Zamani","raw_affiliation_strings":["Amirkabir University of Technology, Tehran, Iran","Amirkabir University of Technology, Tehran, IRAN"],"affiliations":[{"raw_affiliation_string":"Amirkabir University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I158248296"]},{"raw_affiliation_string":"Amirkabir University of Technology, Tehran, IRAN","institution_ids":["https://openalex.org/I158248296"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5047566052"],"corresponding_institution_ids":["https://openalex.org/I158248296"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.13617168,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"265","last_page":"265"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.9072943329811096},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8404408097267151},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.8060318231582642},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.7355852127075195},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6171886324882507},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6093482375144958},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5346646904945374},{"id":"https://openalex.org/keywords/yield","display_name":"Yield (engineering)","score":0.518860936164856},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4661974012851715},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4516425132751465},{"id":"https://openalex.org/keywords/parametric-statistics","display_name":"Parametric statistics","score":0.4507852792739868},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4265025854110718},{"id":"https://openalex.org/keywords/cluster-size","display_name":"Cluster size","score":0.4193841218948364},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.412163645029068},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34243905544281006},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.32897791266441345},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.18951129913330078},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18130749464035034},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16390323638916016},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.1436668038368225},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09528934955596924}],"concepts":[{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.9072943329811096},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8404408097267151},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.8060318231582642},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.7355852127075195},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6171886324882507},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6093482375144958},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5346646904945374},{"id":"https://openalex.org/C134121241","wikidata":"https://www.wikidata.org/wiki/Q899301","display_name":"Yield (engineering)","level":2,"score":0.518860936164856},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4661974012851715},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4516425132751465},{"id":"https://openalex.org/C117251300","wikidata":"https://www.wikidata.org/wiki/Q1849855","display_name":"Parametric statistics","level":2,"score":0.4507852792739868},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4265025854110718},{"id":"https://openalex.org/C3017540586","wikidata":"https://www.wikidata.org/wiki/Q612728","display_name":"Cluster size","level":3,"score":0.4193841218948364},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.412163645029068},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34243905544281006},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.32897791266441345},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.18951129913330078},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18130749464035034},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16390323638916016},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.1436668038368225},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09528934955596924},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C191897082","wikidata":"https://www.wikidata.org/wiki/Q11467","display_name":"Metallurgy","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C86025842","wikidata":"https://www.wikidata.org/wiki/Q5358432","display_name":"Electronic structure","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2145694.2145742","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2145694.2145742","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1978700278","https://openalex.org/W2033443176","https://openalex.org/W2035847677","https://openalex.org/W2084083833","https://openalex.org/W2115596773","https://openalex.org/W2124720785","https://openalex.org/W2126460975","https://openalex.org/W2140468936","https://openalex.org/W2150283124","https://openalex.org/W2161344439","https://openalex.org/W2168296432","https://openalex.org/W2182838578"],"related_works":["https://openalex.org/W3103981520","https://openalex.org/W200972441","https://openalex.org/W2038220260","https://openalex.org/W1857140530","https://openalex.org/W1545578515","https://openalex.org/W1544665014","https://openalex.org/W2098458348","https://openalex.org/W2158008050","https://openalex.org/W2150194641","https://openalex.org/W2128620931"],"abstract_inverted_index":{"Designing":[0],"with":[1,8,133],"field-programmable":[2],"gate":[3],"arrays":[4],"(FPGAs)":[5],"can":[6,56],"face":[7],"difficulties":[9],"due":[10],"to":[11,20,38,52,67,80,87,97,106,112],"process":[12,25],"variations.":[13],"Some":[14],"techniques":[15],"use":[16],"reconfigurability":[17],"of":[18,24,42],"FPGAs":[19,132],"reduce":[21],"the":[22,40],"effects":[23],"variations":[26],"in":[27,100,131],"these":[28],"chips.":[29],"Furthermore,":[30],"FPGA":[31,48],"architecture":[32,55],"enhancement":[33],"is":[34],"an":[35],"effective":[36],"way":[37],"degrade":[39],"impact":[41],"variation.":[43],"In":[44],"this":[45],"paper,":[46],"various":[47],"architectures":[49],"are":[50],"examined":[51],"identify":[53],"which":[54],"achieve":[57],"larger":[58,127,134],"parametric":[59],"yield":[60,82,101,129],"improvement":[61,83,102,130],"utilizing":[62],"multiple":[63],"configurations":[64,110],"as":[65],"opposed":[66],"single":[68,113],"configuration.":[69],"Experimental":[70],"results":[71,99,121],"show":[72],"that":[73,123],"by":[74],"increasing":[75],"cluster":[76,135],"size":[77,94,136],"from":[78,85,95,104],"4":[79,96],"10,":[81],"increases":[84],"2.82X":[86,105],"4.48X.":[88],"However,":[89],"changing":[90],"look-up":[91],"table":[92],"(LUT)":[93],"7":[98],"degradation":[103],"1.45X,":[107],"using":[108],"10":[109],"compared":[111],"configuration":[114],"over":[115],"20":[116],"MCNC":[117],"benchmark":[118],"circuits.":[119],"These":[120],"indicate":[122],"multi-configuration":[124],"technique":[125],"causes":[126],"timing":[128],"and":[137],"smaller":[138],"LUT":[139],"size.":[140]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}