{"id":"https://openalex.org/W2079457862","doi":"https://doi.org/10.1145/2107763.2107769","title":"Optimizing built-in pseudo-random self-testing for network-on-chip switches","display_name":"Optimizing built-in pseudo-random self-testing for network-on-chip switches","publication_year":2012,"publication_date":"2012-01-24","ids":{"openalex":"https://openalex.org/W2079457862","doi":"https://doi.org/10.1145/2107763.2107769","mag":"2079457862"},"language":"en","primary_location":{"id":"doi:10.1145/2107763.2107769","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2107763.2107769","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051021139","display_name":"Simone Terenzi","orcid":null},"institutions":[{"id":"https://openalex.org/I201324441","display_name":"University of Ferrara","ror":"https://ror.org/041zkgm14","country_code":"IT","type":"education","lineage":["https://openalex.org/I201324441"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Simone Terenzi","raw_affiliation_strings":["ENDIF, University of Ferrara, Ferrara, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ENDIF, University of Ferrara, Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027446961","display_name":"Alessandro Strano","orcid":null},"institutions":[{"id":"https://openalex.org/I201324441","display_name":"University of Ferrara","ror":"https://ror.org/041zkgm14","country_code":"IT","type":"education","lineage":["https://openalex.org/I201324441"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alessandro Strano","raw_affiliation_strings":["ENDIF, University of Ferrara, Ferrara, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ENDIF, University of Ferrara, Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011268330","display_name":"Davide Bertozzi","orcid":"https://orcid.org/0000-0001-7462-4551"},"institutions":[{"id":"https://openalex.org/I201324441","display_name":"University of Ferrara","ror":"https://ror.org/041zkgm14","country_code":"IT","type":"education","lineage":["https://openalex.org/I201324441"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Davide Bertozzi","raw_affiliation_strings":["ENDIF, University of Ferrara, Ferrara, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ENDIF, University of Ferrara, Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I201324441"],"apc_list":null,"apc_paid":null,"fwci":0.8489,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.70430553,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"21","last_page":"24"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/random-testing","display_name":"Random testing","score":0.7461236119270325},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7373687624931335},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.6074830889701843},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.598385751247406},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5686394572257996},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5259837508201599},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.49667221307754517},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.47017306089401245},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.45362111926078796},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4388183057308197},{"id":"https://openalex.org/keywords/white-box-testing","display_name":"White-box testing","score":0.4299444556236267},{"id":"https://openalex.org/keywords/test-strategy","display_name":"Test strategy","score":0.41810792684555054},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4148993194103241},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.32298168540000916},{"id":"https://openalex.org/keywords/test-case","display_name":"Test case","score":0.2852574288845062},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.17240765690803528},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13784566521644592},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.09326127171516418}],"concepts":[{"id":"https://openalex.org/C106159264","wikidata":"https://www.wikidata.org/wiki/Q17146789","display_name":"Random testing","level":4,"score":0.7461236119270325},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7373687624931335},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.6074830889701843},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.598385751247406},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5686394572257996},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5259837508201599},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.49667221307754517},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.47017306089401245},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.45362111926078796},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4388183057308197},{"id":"https://openalex.org/C162443782","wikidata":"https://www.wikidata.org/wiki/Q1066228","display_name":"White-box testing","level":5,"score":0.4299444556236267},{"id":"https://openalex.org/C188598960","wikidata":"https://www.wikidata.org/wiki/Q7705805","display_name":"Test strategy","level":3,"score":0.41810792684555054},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4148993194103241},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32298168540000916},{"id":"https://openalex.org/C128942645","wikidata":"https://www.wikidata.org/wiki/Q1568346","display_name":"Test case","level":3,"score":0.2852574288845062},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.17240765690803528},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13784566521644592},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.09326127171516418},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C152877465","wikidata":"https://www.wikidata.org/wiki/Q208042","display_name":"Regression analysis","level":2,"score":0.0},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/2107763.2107769","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2107763.2107769","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop","raw_type":"proceedings-article"},{"id":"pmh:oai:iris.unife.it:11392/1736312","is_oa":false,"landing_page_url":"http://hdl.handle.net/11392/1736312","pdf_url":null,"source":{"id":"https://openalex.org/S4306400369","display_name":"Institutional Research Information System University of Ferrara (University of Ferrara)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I201324441","host_organization_name":"University of Ferrara","host_organization_lineage":["https://openalex.org/I201324441"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"No poverty","score":0.4099999964237213,"id":"https://metadata.un.org/sdg/1"}],"awards":[{"id":"https://openalex.org/G8243993830","display_name":null,"funder_award_id":"FP7-ICT-248972","funder_id":"https://openalex.org/F4320334960","funder_display_name":"Seventh Framework Programme"}],"funders":[{"id":"https://openalex.org/F4320334960","display_name":"Seventh Framework Programme","ror":"https://ror.org/00k4n6c32"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W626927905","https://openalex.org/W1600358781","https://openalex.org/W1981991312","https://openalex.org/W2026037646","https://openalex.org/W2073742560","https://openalex.org/W2106053735","https://openalex.org/W2119264875","https://openalex.org/W2125231919","https://openalex.org/W2128436801","https://openalex.org/W2131294178","https://openalex.org/W2164203755"],"related_works":["https://openalex.org/W2104478015","https://openalex.org/W4230343699","https://openalex.org/W2061526428","https://openalex.org/W2127857760","https://openalex.org/W2535722923","https://openalex.org/W175503027","https://openalex.org/W1591681788","https://openalex.org/W2160942127","https://openalex.org/W2955592476","https://openalex.org/W4399433292"],"abstract_inverted_index":{"Most":[0],"BIST":[1],"architectures":[2],"use":[3,43],"pseudo-random":[4,71],"test":[5,46,72,93],"pattern":[6],"generators.":[7],"However,":[8],"whenever":[9],"this":[10],"technique":[11],"has":[12],"been":[13,24],"applied":[14],"to":[15,74],"on-chip":[16],"interconnection":[17],"networks,":[18],"overly":[19],"large":[20,35],"testing":[21,40,86],"latencies":[22],"have":[23],"reported.":[25],"On":[26],"the":[27,42,54,62,75],"other":[28],"hand,":[29],"alternative":[30],"approaches":[31],"either":[32],"suffer":[33],"from":[34],"area":[36,98],"penalties":[37],"(like":[38],"scan-based":[39],"or":[41,48],"of":[44,51,64,77],"deterministic":[45,92],"patterns)":[47],"poor":[49],"coverage":[50,84],"faults":[52],"in":[53],"control":[55],"path":[56],"(functional":[57],"testing).":[58],"This":[59],"paper":[60],"presents":[61],"optimization":[63],"a":[65,81],"built-in":[66],"self-testing":[67],"framework":[68],"based":[69],"on":[70],"patterns":[73,94],"microarchitecture":[76],"network-on-chip":[78],"switches.":[79],"As":[80],"result,":[82],"fault":[83],"and":[85,100],"latency":[87],"approach":[88],"those":[89],"achievable":[90],"with":[91],"while":[95],"materializing":[96],"relevant":[97],"savings":[99],"enhanced":[101],"flexibility.":[102]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
