{"id":"https://openalex.org/W2076688601","doi":"https://doi.org/10.1145/2076501.2076508","title":"Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip","display_name":"Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip","publication_year":2011,"publication_date":"2011-12-04","ids":{"openalex":"https://openalex.org/W2076688601","doi":"https://doi.org/10.1145/2076501.2076508","mag":"2076688601"},"language":"en","primary_location":{"id":"doi:10.1145/2076501.2076508","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2076501.2076508","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 4th International Workshop on Network on Chip Architectures","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113405673","display_name":"D\u00e9bora Matos","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Debora Matos","raw_affiliation_strings":["UFRGS Institute of Informatics, Porto Alegre, Brazil","UFRGS -- Institute of Informatics, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"UFRGS Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"UFRGS -- Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077005193","display_name":"Gianluca Palermo","orcid":"https://orcid.org/0000-0001-7955-8012"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gianluca Palermo","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086350616","display_name":"Vittorio Zaccaria","orcid":"https://orcid.org/0000-0001-5685-9795"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Vittorio Zaccaria","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019414171","display_name":"Cezar Reinbrecht","orcid":"https://orcid.org/0000-0001-6113-7041"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Cezar Reinbrecht","raw_affiliation_strings":["UFRGS Institute of Informatics, Porto Alegre, Brazil","UFRGS -- Institute of Informatics, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"UFRGS Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"UFRGS -- Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043190662","display_name":"Altamiro Susin","orcid":"https://orcid.org/0000-0001-7034-5336"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Altamiro Susin","raw_affiliation_strings":["UFRGS Institute of Informatics, Porto Alegre, Brazil","UFRGS -- Institute of Informatics, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"UFRGS Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"UFRGS -- Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031461662","display_name":"Cristina Silvano","orcid":"https://orcid.org/0000-0003-1668-0883"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Cristina Silvano","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062358729","display_name":"Luigi Carro","orcid":"https://orcid.org/0000-0002-7402-4780"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Luigi Carro","raw_affiliation_strings":["UFRGS Institute of Informatics, Porto Alegre, Brazil","UFRGS -- Institute of Informatics, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"UFRGS Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"UFRGS -- Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5113405673"],"corresponding_institution_ids":["https://openalex.org/I130442723"],"apc_list":null,"apc_paid":null,"fwci":1.8271,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.86124446,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"31","last_page":"36"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9934999942779541,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.987500011920929,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.8092606663703918},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.763953447341919},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6751806735992432},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6350993514060974},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.6100195646286011},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.6049565076828003},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5795115232467651},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5731959939002991},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5439316034317017},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.46505317091941833},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4646781086921692},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4338530898094177},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4187556505203247},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4016014337539673},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.36118632555007935},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3523982763290405},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33064574003219604},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10286378860473633}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.8092606663703918},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.763953447341919},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6751806735992432},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6350993514060974},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.6100195646286011},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.6049565076828003},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5795115232467651},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5731959939002991},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5439316034317017},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.46505317091941833},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4646781086921692},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4338530898094177},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4187556505203247},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4016014337539673},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.36118632555007935},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3523982763290405},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33064574003219604},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10286378860473633}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/2076501.2076508","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2076501.2076508","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 4th International Workshop on Network on Chip Architectures","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.471.476","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.471.476","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://home.deib.polimi.it/zaccaria/VZ/pdf/C38.pdf","raw_type":"text"},{"id":"pmh:oai:re.public.polimi.it:11311/633666","is_oa":false,"landing_page_url":"http://doi.acm.org/10.1145/2076501.2076508","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1501077214","https://openalex.org/W1564285798","https://openalex.org/W1973645408","https://openalex.org/W2082603453","https://openalex.org/W2119499507","https://openalex.org/W2120024496","https://openalex.org/W2124449277","https://openalex.org/W2132249049","https://openalex.org/W2156954907","https://openalex.org/W2157599482","https://openalex.org/W2166151045","https://openalex.org/W2167159964","https://openalex.org/W3165267979"],"related_works":["https://openalex.org/W4230458348","https://openalex.org/W3198758847","https://openalex.org/W4234221021","https://openalex.org/W1973069902","https://openalex.org/W2119904701","https://openalex.org/W2119674509","https://openalex.org/W2975035977","https://openalex.org/W2169248084","https://openalex.org/W2026454041","https://openalex.org/W2533063779"],"abstract_inverted_index":{"Application-specific":[0],"network-centric":[1],"architectures":[2,58,68],"(such":[3],"as":[4],"Networks":[5],"on-Chip,":[6],"NoCs)":[7],"have":[8],"recently":[9],"become":[10],"an":[11,140,155],"effective":[12],"solution":[13],"to":[14,51,138,162],"support":[15],"high":[16],"bandwidth":[17],"communication":[18,42,72],"in":[19,30,43,115],"Multiprocessor":[20],"Systems-on-Chip":[21],"(MPSoCs).":[22],"Moreover,":[23],"the":[24,27,31,36,41,70,81,99,104,108,112,126,133],"introduction":[25],"of":[26,40,111,117,146,154,158],"hierarchy":[28],"concept":[29],"NoC":[32,56],"design":[33,52,96],"benefits":[34],"from":[35,103],"main":[37],"locality":[38],"nature":[39],"MPSoC":[44],"architectures.":[45],"This":[46],"paper":[47],"presents":[48],"a":[49,76,87,152,163],"methodology":[50],"Application":[53],"Specific":[54],"Hierarchical":[55],"(ASHiNoC)":[57],"considering":[59],"foorplanning":[60],"information.":[61],"The":[62,94],"presented":[63],"approach":[64],"targets":[65],"heterogeneous":[66],"clustered":[67],"where":[69],"intra-cluster":[71],"is":[73,136],"managed":[74,85],"by":[75,86,101],"low-latency":[77],"circuit-switched":[78],"crossbar,":[79],"while":[80],"inter-cluster":[82],"communications":[83],"are":[84],"high-bandwidth":[88],"packet-based":[89],"NoC,":[90],"allowing":[91],"regulars":[92],"topologies.":[93],"proposed":[95],"flow":[97],"faces":[98],"problem":[100],"starting":[102],"cluster":[105,123],"selection":[106],"down-to":[107],"foorplanning-aware":[109],"estimation":[110],"interconnect":[113],"performances":[114],"terms":[116],"latency,":[118],"power,":[119],"area":[120,156],"within":[121],"each":[122],"and":[124,143,148],"for":[125],"backbone":[127],"NoC.":[128],"Experimental":[129],"results":[130],"show":[131],"that":[132],"AHiNoC":[134],"architecture":[135],"able":[137],"guarantee":[139],"interconnection":[141],"power":[142],"latency":[144],"reduction":[145],"49%":[147],"33%":[149],"respectively,":[150],"at":[151],"cost":[153],"increment":[157],"78%":[159],"with":[160],"respect":[161],"flat":[164],"topology":[165],"version.":[166]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
