{"id":"https://openalex.org/W2083030004","doi":"https://doi.org/10.1145/2068716.2068721","title":"FPGA technology mapping with encoded libraries and staged priority cuts","display_name":"FPGA technology mapping with encoded libraries and staged priority cuts","publication_year":2011,"publication_date":"2011-12-01","ids":{"openalex":"https://openalex.org/W2083030004","doi":"https://doi.org/10.1145/2068716.2068721","mag":"2083030004"},"language":"en","primary_location":{"id":"doi:10.1145/2068716.2068721","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2068716.2068721","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007026340","display_name":"Andrew Kennings","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Andrew Kennings","raw_affiliation_strings":["Actel Corporation, Mountain View, CA"],"affiliations":[{"raw_affiliation_string":"Actel Corporation, Mountain View, CA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005615652","display_name":"Kristofer Vorwerk","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kristofer Vorwerk","raw_affiliation_strings":["Actel Corporation, Mountain View, CA"],"affiliations":[{"raw_affiliation_string":"Actel Corporation, Mountain View, CA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111625464","display_name":"Arun Kundu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Arun Kundu","raw_affiliation_strings":["Actel Corporation, Mountain View, CA"],"affiliations":[{"raw_affiliation_string":"Actel Corporation, Mountain View, CA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070951209","display_name":"Val Pevzner","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Val Pevzner","raw_affiliation_strings":["Actel Corporation, Mountain View, CA"],"affiliations":[{"raw_affiliation_string":"Actel Corporation, Mountain View, CA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025559864","display_name":"Andy Fox","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Andy Fox","raw_affiliation_strings":["Actel Corporation, Mountain View, CA"],"affiliations":[{"raw_affiliation_string":"Actel Corporation, Mountain View, CA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5007026340"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.12561344,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":"4","issue":"4","first_page":"1","last_page":"17"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.8807200193405151},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8306650519371033},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8289430141448975},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.751446008682251},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5759828090667725},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5255200862884521},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4770064651966095},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.458636611700058},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4298231601715088},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.42143160104751587},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.41591811180114746},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4041231870651245},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38702476024627686},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3228520154953003},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09854722023010254}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.8807200193405151},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8306650519371033},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8289430141448975},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.751446008682251},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5759828090667725},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5255200862884521},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4770064651966095},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.458636611700058},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4298231601715088},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42143160104751587},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.41591811180114746},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4041231870651245},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38702476024627686},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3228520154953003},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09854722023010254},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2068716.2068721","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2068716.2068721","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5899999737739563,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1480183640","https://openalex.org/W1612810659","https://openalex.org/W1905608265","https://openalex.org/W1985457698","https://openalex.org/W2003435315","https://openalex.org/W2035561773","https://openalex.org/W2052067881","https://openalex.org/W2089442786","https://openalex.org/W2096466247","https://openalex.org/W2099134576","https://openalex.org/W2100955320","https://openalex.org/W2105715355","https://openalex.org/W2108508582","https://openalex.org/W2116094656","https://openalex.org/W2118988958","https://openalex.org/W2122498441","https://openalex.org/W2133743520","https://openalex.org/W2134057731","https://openalex.org/W2134060873","https://openalex.org/W2139026138","https://openalex.org/W2150787480","https://openalex.org/W2159111323","https://openalex.org/W2163492764","https://openalex.org/W2294502317","https://openalex.org/W4236504040","https://openalex.org/W4240866746","https://openalex.org/W6600106573","https://openalex.org/W6674369357"],"related_works":["https://openalex.org/W2366554144","https://openalex.org/W2024574431","https://openalex.org/W4239932082","https://openalex.org/W2107701025","https://openalex.org/W2083030004","https://openalex.org/W2182005210","https://openalex.org/W2105584319","https://openalex.org/W2594026766","https://openalex.org/W3176821810","https://openalex.org/W2000448684"],"abstract_inverted_index":{"Technology":[0],"mapping":[1,34],"is":[2,18,59,78],"an":[3,37],"important":[4],"step":[5],"in":[6,11],"the":[7,56,75,100,103],"FPGA":[8,38,113],"CAD":[9],"flow":[10],"which":[12,43,98],"a":[13,21,31,46,60,69,111],"network":[14,22],"of":[15,23,40,48,50,74,102],"simple":[16],"gates":[17],"converted":[19],"into":[20],"logic":[24,41,57,76],"blocks.":[25],"This":[26],"article":[27],"considers":[28],"enhancements":[29],"to":[30,52,110],"traditional":[32],"LUT-based":[33],"algorithm":[35],"for":[36,82],"comprised":[39],"blocks":[42],"implement":[44],"only":[45],"subset":[47],"functions":[49],"up":[51],"k":[53],"variables;":[54],"specifically,":[55],"block":[58,77],"partial":[61],"LUT,":[62],"but":[63],"it":[64],"possesses":[65],"more":[66],"inputs":[67],"than":[68],"typical":[70],"LUT.":[71],"An":[72],"analysis":[73],"presented,":[79],"and":[80,86],"techniques":[81],"postmapping":[83],"area":[84],"recovery":[85],"timing-driven":[87],"buffer":[88],"insertion":[89],"are":[90,95],"also":[91],"described.":[92],"Numerical":[93],"results":[94],"put":[96],"forth":[97],"substantiate":[99],"efficacy":[101],"proposed":[104],"methods":[105],"using":[106],"real":[107],"circuits":[108],"mapped":[109],"commercial":[112],"architecture.":[114]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
