{"id":"https://openalex.org/W2151310824","doi":"https://doi.org/10.1145/2039370.2039381","title":"A design methodology to implement memory accesses in high-level synthesis","display_name":"A design methodology to implement memory accesses in high-level synthesis","publication_year":2011,"publication_date":"2011-10-09","ids":{"openalex":"https://openalex.org/W2151310824","doi":"https://doi.org/10.1145/2039370.2039381","mag":"2151310824"},"language":"en","primary_location":{"id":"doi:10.1145/2039370.2039381","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2039370.2039381","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072400487","display_name":"Christian Pilato","orcid":"https://orcid.org/0000-0001-9315-1788"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Christian Pilato","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028565685","display_name":"Fabrizio Ferrandi","orcid":"https://orcid.org/0000-0003-0301-4419"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Fabrizio Ferrandi","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014181688","display_name":"Donatella Sciuto","orcid":"https://orcid.org/0000-0001-9030-6940"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Donatella Sciuto","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":25,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"49","last_page":"58"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8380882143974304},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7132005095481873},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.7096587419509888},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5401555299758911},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5046802759170532},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.48950517177581787},{"id":"https://openalex.org/keywords/high-level-design","display_name":"High-level design","score":0.4879269301891327},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3579680919647217},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3294920027256012},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3201766312122345},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2931661009788513},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.19262343645095825},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.1468266248703003},{"id":"https://openalex.org/keywords/iterative-design","display_name":"Iterative design","score":0.07245028018951416},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07134363055229187}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8380882143974304},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7132005095481873},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.7096587419509888},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5401555299758911},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5046802759170532},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.48950517177581787},{"id":"https://openalex.org/C78246475","wikidata":"https://www.wikidata.org/wiki/Q5754546","display_name":"High-level design","level":4,"score":0.4879269301891327},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3579680919647217},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3294920027256012},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3201766312122345},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2931661009788513},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.19262343645095825},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.1468266248703003},{"id":"https://openalex.org/C106246047","wikidata":"https://www.wikidata.org/wiki/Q4928435","display_name":"Iterative design","level":3,"score":0.07245028018951416},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07134363055229187},{"id":"https://openalex.org/C2778648169","wikidata":"https://www.wikidata.org/wiki/Q967768","display_name":"Compatibility (geochemistry)","level":2,"score":0.0},{"id":"https://openalex.org/C42360764","wikidata":"https://www.wikidata.org/wiki/Q83588","display_name":"Chemical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/2039370.2039381","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2039370.2039381","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/608571","is_oa":false,"landing_page_url":"http://hdl.handle.net/11311/608571","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1994115836","https://openalex.org/W2018055497","https://openalex.org/W2057807751","https://openalex.org/W2089419262","https://openalex.org/W2095643031","https://openalex.org/W2100724742","https://openalex.org/W2103581911","https://openalex.org/W2123599378","https://openalex.org/W2128544270","https://openalex.org/W2129183345","https://openalex.org/W2153407319","https://openalex.org/W2161065509","https://openalex.org/W2171133986"],"related_works":["https://openalex.org/W2135482679","https://openalex.org/W2035070505","https://openalex.org/W2000188956","https://openalex.org/W1973862904","https://openalex.org/W3149594966","https://openalex.org/W181593118","https://openalex.org/W2296236528","https://openalex.org/W1966826470","https://openalex.org/W4281926497","https://openalex.org/W3022794856"],"abstract_inverted_index":{"Nowadays,":[0],"the":[1,6,10,34,53,59],"memory":[2,27,54],"synthesis":[3],"is":[4],"becoming":[5],"main":[7],"bottleneck":[8],"for":[9],"generation":[11],"of":[12,48,58],"efficient":[13],"hardware":[14],"accelerators.":[15],"This":[16],"paper":[17],"presents":[18],"a":[19,38,46],"design":[20,49],"methodology":[21],"to":[22],"efficiently":[23],"and":[24,45],"automatically":[25],"implement":[26],"accesses":[28],"in":[29],"High-Level":[30],"Synthesis.":[31],"In":[32],"particular,":[33],"approach":[35],"starts":[36],"from":[37],"behavioral":[39],"specification":[40],"(in":[41],"pure":[42],"C":[43],"language)":[44],"set":[47],"constraints,":[50],"such":[51],"as":[52],"addresses":[55],"where":[56],"some":[57],"data":[60],"are":[61],"stored.":[62]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":7},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}