{"id":"https://openalex.org/W2139817798","doi":"https://doi.org/10.1145/2038698.2038728","title":"An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture","display_name":"An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture","publication_year":2011,"publication_date":"2011-10-09","ids":{"openalex":"https://openalex.org/W2139817798","doi":"https://doi.org/10.1145/2038698.2038728","mag":"2139817798"},"language":"en","primary_location":{"id":"doi:10.1145/2038698.2038728","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2038698.2038728","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016370549","display_name":"Ricardo Ferreira","orcid":"https://orcid.org/0000-0003-1802-7829"},"institutions":[{"id":"https://openalex.org/I146165071","display_name":"Universidade Federal de Vi\u00e7osa","ror":"https://ror.org/0409dgb37","country_code":"BR","type":"education","lineage":["https://openalex.org/I146165071"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Ricardo Ferreira","raw_affiliation_strings":["Universidade Federal de Vicosa, Vicosa, Brazil","Departamento de Informatica, Universidade Federal de Vicosa, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidade Federal de Vicosa, Vicosa, Brazil","institution_ids":["https://openalex.org/I146165071"]},{"raw_affiliation_string":"Departamento de Informatica, Universidade Federal de Vicosa, Brazil","institution_ids":["https://openalex.org/I146165071"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111947671","display_name":"Julio Vendramini","orcid":null},"institutions":[{"id":"https://openalex.org/I146165071","display_name":"Universidade Federal de Vi\u00e7osa","ror":"https://ror.org/0409dgb37","country_code":"BR","type":"education","lineage":["https://openalex.org/I146165071"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Julio Goldner Vendramini","raw_affiliation_strings":["Universidade Federal de Vicosa, Vicosa, Brazil","Departamento de Informatica, Universidade Federal de Vicosa, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidade Federal de Vicosa, Vicosa, Brazil","institution_ids":["https://openalex.org/I146165071"]},{"raw_affiliation_string":"Departamento de Informatica, Universidade Federal de Vicosa, Brazil","institution_ids":["https://openalex.org/I146165071"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010962040","display_name":"Lucas Mucida","orcid":null},"institutions":[{"id":"https://openalex.org/I146165071","display_name":"Universidade Federal de Vi\u00e7osa","ror":"https://ror.org/0409dgb37","country_code":"BR","type":"education","lineage":["https://openalex.org/I146165071"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Lucas Mucida","raw_affiliation_strings":["Universidade Federal de Vicosa, Vicosa, Brazil","Departamento de Informatica, Universidade Federal de Vicosa, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidade Federal de Vicosa, Vicosa, Brazil","institution_ids":["https://openalex.org/I146165071"]},{"raw_affiliation_string":"Departamento de Informatica, Universidade Federal de Vicosa, Brazil","institution_ids":["https://openalex.org/I146165071"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103034522","display_name":"Monica Pereira","orcid":"https://orcid.org/0000-0002-6580-1250"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Monica Magalhaes Pereira","raw_affiliation_strings":["Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil","Instituto de Informatica-PPGC, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Instituto de Informatica-PPGC, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062358729","display_name":"Luigi Carro","orcid":"https://orcid.org/0000-0002-7402-4780"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Luigi Carro","raw_affiliation_strings":["Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil","Instituto de Informatica-PPGC, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Instituto de Informatica-PPGC, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.3301,"has_fulltext":false,"cited_by_count":29,"citation_normalized_percentile":{"value":0.80181984,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"195","last_page":"204"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.825377345085144},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.7308257818222046},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7131121158599854},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6134575009346008},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5180845260620117},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5133761167526245},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.4907897412776947},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.4889453649520874},{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.47406405210494995},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.424399197101593},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.42055171728134155},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37737417221069336},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3739825487136841},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1521294116973877}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.825377345085144},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.7308257818222046},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7131121158599854},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6134575009346008},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5180845260620117},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5133761167526245},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.4907897412776947},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4889453649520874},{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.47406405210494995},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.424399197101593},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.42055171728134155},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37737417221069336},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3739825487136841},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1521294116973877},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2038698.2038728","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2038698.2038728","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320320875","display_name":"Deutscher Akademischer Austauschdienst","ror":"https://ror.org/039djdh30"},{"id":"https://openalex.org/F4320321091","display_name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior","ror":"https://ror.org/00x0ma614"},{"id":"https://openalex.org/F4320322987","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1561770367","https://openalex.org/W1585554789","https://openalex.org/W1912842061","https://openalex.org/W1995750454","https://openalex.org/W2013505463","https://openalex.org/W2025787141","https://openalex.org/W2045998385","https://openalex.org/W2096313289","https://openalex.org/W2100927806","https://openalex.org/W2101705466","https://openalex.org/W2112136590","https://openalex.org/W2116304229","https://openalex.org/W2118007759","https://openalex.org/W2123412205","https://openalex.org/W2134111163","https://openalex.org/W2134316164","https://openalex.org/W2135050419","https://openalex.org/W2137570657","https://openalex.org/W2139637699","https://openalex.org/W2159736365","https://openalex.org/W2275304190","https://openalex.org/W2544237667","https://openalex.org/W2554510265","https://openalex.org/W6818140485","https://openalex.org/W7020824226"],"related_works":["https://openalex.org/W2152623100","https://openalex.org/W25204318","https://openalex.org/W2096417281","https://openalex.org/W2138895528","https://openalex.org/W2077035242","https://openalex.org/W3042643149","https://openalex.org/W2026481470","https://openalex.org/W1999203047","https://openalex.org/W3201977823","https://openalex.org/W2362203107"],"abstract_inverted_index":{"Coarse-grained":[0],"reconfigurable":[1],"architecture":[2,76],"has":[3,34],"emerged":[4],"as":[5,12],"a":[6,13,48,79,87,113,130,159],"promising":[7],"model":[8],"for":[9,158],"embedded":[10],"systems":[11],"solution":[14],"to":[15,38,97,138],"reduce":[16],"the":[17,39,62,70,106,126],"complexity":[18],"of":[19,41,56,64,72,78,81,153,161],"FPGA":[20,66],"synthesis":[21],"and":[22,50,86,121,134],"mapping":[23,115],"steps,":[24],"consequently":[25],"reducing":[26],"reconfiguration":[27],"time.":[28],"Despite":[29],"these":[30],"advantages,":[31],"CGRA":[32,43,52,140],"usage":[33,63],"been":[35],"limited":[36],"due":[37],"lack":[40],"commercial":[42],"circuits.":[44],"This":[45,59],"work":[46],"proposes":[47],"virtual":[49],"dynamic":[51],"implemented":[53],"on":[54],"top":[55],"an":[57],"FPGA.":[58],"approach":[60,128,155],"allows":[61,94],"commercial-off-the-shelf":[65],"devices":[67],"combined":[68],"with":[69],"advantages":[71],"CGRAs.":[73],"The":[74,91,142,151],"proposed":[75,127],"consists":[77],"set":[80],"heterogeneous":[82],"functional":[83],"units":[84],"(FU)":[85],"global":[88,92],"interconnection":[89],"network.":[90],"network":[93],"any":[95],"FU":[96],"be":[98],"used":[99],"at":[100],"each":[101],"cycle,":[102],"which":[103,117],"reduces":[104],"significantly":[105],"placement":[107,120,133],"complexity.":[108],"In":[109],"addition,":[110],"we":[111],"introduce":[112],"polynomial":[114],"algorithm":[116],"includes":[118],"scheduling,":[119],"routing":[122,135],"steps":[123,145],"(SPR).":[124],"Moreover,":[125],"performs":[129],"very":[131],"fast":[132],"in":[136,148],"comparison":[137],"similar":[139],"approaches.":[141],"three":[143],"SPR":[144],"are":[146],"computed":[147],"few":[149],"milliseconds.":[150],"feasibility":[152],"this":[154],"is":[156],"demonstrated":[157],"suite":[160],"digital":[162],"signal":[163],"processing":[164],"benchmarks.":[165]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":4}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
