{"id":"https://openalex.org/W4245183599","doi":"https://doi.org/10.1145/2034773.2034804","title":"Deriving an efficient FPGA implementation of a low density parity check forward error corrector","display_name":"Deriving an efficient FPGA implementation of a low density parity check forward error corrector","publication_year":2011,"publication_date":"2011-09-19","ids":{"openalex":"https://openalex.org/W4245183599","doi":"https://doi.org/10.1145/2034773.2034804"},"language":"en","primary_location":{"id":"doi:10.1145/2034773.2034804","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2034773.2034804","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 16th ACM SIGPLAN international conference on Functional programming","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029124439","display_name":"Andy Gill","orcid":null},"institutions":[{"id":"https://openalex.org/I146416000","display_name":"University of Kansas","ror":"https://ror.org/001tmjg57","country_code":"US","type":"education","lineage":["https://openalex.org/I146416000"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andy Gill","raw_affiliation_strings":["University of Kansas, Lawrence, KS, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Kansas, Lawrence, KS, USA","institution_ids":["https://openalex.org/I146416000"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077194053","display_name":"Andrew Farmer","orcid":"https://orcid.org/0000-0002-4224-2433"},"institutions":[{"id":"https://openalex.org/I146416000","display_name":"University of Kansas","ror":"https://ror.org/001tmjg57","country_code":"US","type":"education","lineage":["https://openalex.org/I146416000"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andrew Farmer","raw_affiliation_strings":["University of Kansas, Lawrence, KS, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Kansas, Lawrence, KS, USA","institution_ids":["https://openalex.org/I146416000"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I146416000"],"apc_list":null,"apc_paid":null,"fwci":1.7903,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.86106363,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"209","last_page":"220"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8182810544967651},{"id":"https://openalex.org/keywords/executable","display_name":"Executable","score":0.7229791879653931},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.689263105392456},{"id":"https://openalex.org/keywords/haskell","display_name":"Haskell","score":0.6767367124557495},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.6063423156738281},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5906505584716797},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.5387630462646484},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.4612395465373993},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.4464876651763916},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.37235385179519653},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3201691508293152},{"id":"https://openalex.org/keywords/functional-programming","display_name":"Functional programming","score":0.2764037549495697},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.23981532454490662}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8182810544967651},{"id":"https://openalex.org/C160145156","wikidata":"https://www.wikidata.org/wiki/Q778586","display_name":"Executable","level":2,"score":0.7229791879653931},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.689263105392456},{"id":"https://openalex.org/C2780624054","wikidata":"https://www.wikidata.org/wiki/Q34010","display_name":"Haskell","level":3,"score":0.6767367124557495},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.6063423156738281},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5906505584716797},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5387630462646484},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.4612395465373993},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.4464876651763916},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.37235385179519653},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3201691508293152},{"id":"https://openalex.org/C42383842","wikidata":"https://www.wikidata.org/wiki/Q193076","display_name":"Functional programming","level":2,"score":0.2764037549495697},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.23981532454490662}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2034773.2034804","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2034773.2034804","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 16th ACM SIGPLAN international conference on Functional programming","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41999998688697815,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320332808","display_name":"Smithsonian Tropical Research Institute","ror":"https://ror.org/035jbxr46"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1965784613","https://openalex.org/W1990403418","https://openalex.org/W1996307546","https://openalex.org/W2000212732","https://openalex.org/W2003131643","https://openalex.org/W2018014973","https://openalex.org/W2023299380","https://openalex.org/W2049600101","https://openalex.org/W2103705529","https://openalex.org/W2107214848","https://openalex.org/W2118165414","https://openalex.org/W2138452186","https://openalex.org/W2168609733","https://openalex.org/W3023216518","https://openalex.org/W4300188436","https://openalex.org/W6607057251","https://openalex.org/W6678839936"],"related_works":["https://openalex.org/W2801835562","https://openalex.org/W196828063","https://openalex.org/W4247743232","https://openalex.org/W4238447024","https://openalex.org/W1602185604","https://openalex.org/W2911281194","https://openalex.org/W1484777401","https://openalex.org/W2390807153","https://openalex.org/W2529830312","https://openalex.org/W2188055041"],"abstract_inverted_index":{"Creating":[0],"correct":[1,48],"hardware":[2],"is":[3,7,87],"hard.":[4],"Though":[5],"there":[6],"much":[8],"talk":[9],"of":[10,30,46,53,60],"using":[11,92,103],"formal":[12,32,69],"and":[13,19,56,101],"semi-formal":[14,34,93],"methods":[15],"to":[16,81],"develop":[17],"designs":[18],"implementations,":[20],"in":[21,76],"practice":[22],"most":[23],"implementations":[24],"are":[25],"written":[26,75],"without":[27],"the":[28,51,58,77,98],"support":[29],"any":[31],"or":[33],"methodology.":[35],"Having":[36],"such":[37],"a":[38,47,67,111,128],"methodology":[39,70,109],"brings":[40],"many":[41],"benefits,":[42],"including":[43],"improved":[44],"likelihood":[45],"implementation,":[49],"lowering":[50,57],"cost":[52,59],"design":[54],"exploration":[55],"certification.":[61],"In":[62],"this":[63],"paper,":[64],"we":[65],"introduce":[66],"semi":[68],"for":[71],"connecting":[72],"executable":[73],"specifications":[74],"functional":[78],"language":[79],"Haskell":[80],"efficient":[82,115],"VHDL":[83],"implementations.":[84],"The":[85],"connection":[86],"performed":[88],"by":[89,97],"manual":[90],"edits,":[91],"equational":[94],"reasoning":[95],"facilitated":[96],"worker/wrapper":[99],"transformation,":[100],"directed":[102],"commutable":[104],"functors.":[105],"We":[106],"explain":[107],"our":[108],"on":[110,127],"full-scale":[112],"example,":[113],"an":[114],"Low-Density":[116],"Parity":[117],"Check":[118],"forward":[119],"error":[120],"correcting":[121],"code,":[122],"which":[123],"has":[124],"been":[125],"implemented":[126],"Virtex-5":[129],"FPGA.":[130]},"counts_by_year":[{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-07-30T17:31:21.811387","created_date":"2025-10-10T00:00:00"}
