{"id":"https://openalex.org/W2014468639","doi":"https://doi.org/10.1145/2019608.2019609","title":"Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs","display_name":"Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2014468639","doi":"https://doi.org/10.1145/2019608.2019609","mag":"2014468639"},"language":"en","primary_location":{"id":"doi:10.1145/2019608.2019609","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2019608.2019609","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/2019608.2019609","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://dl.acm.org/doi/pdf/10.1145/2019608.2019609","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012942261","display_name":"Xi E. Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Xi E. Chen","raw_affiliation_strings":["University of British Columbia, Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026788167","display_name":"Tor M. Aamodt","orcid":"https://orcid.org/0000-0003-1161-692X"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Tor M. Aamodt","raw_affiliation_strings":["University of British Columbia, Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":1.0306,"has_fulltext":true,"cited_by_count":15,"citation_normalized_percentile":{"value":0.77555903,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"8","issue":"3","first_page":"1","last_page":"28"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8732787370681763},{"id":"https://openalex.org/keywords/superscalar","display_name":"Superscalar","score":0.7404609322547913},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.688614010810852},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6670362949371338},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.642561674118042},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5697829723358154},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.49814891815185547},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4877258241176605},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.22436252236366272},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.15151682496070862},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.09542092680931091},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.07829049229621887}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8732787370681763},{"id":"https://openalex.org/C147101560","wikidata":"https://www.wikidata.org/wiki/Q1045706","display_name":"Superscalar","level":2,"score":0.7404609322547913},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.688614010810852},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6670362949371338},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.642561674118042},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5697829723358154},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.49814891815185547},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4877258241176605},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.22436252236366272},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.15151682496070862},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.09542092680931091},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.07829049229621887},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/2019608.2019609","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2019608.2019609","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/2019608.2019609","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.565.879","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.565.879","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.ubc.ca/~xichen/xichen.micro2008.pdf","raw_type":"text"}],"best_oa_location":{"id":"doi:10.1145/2019608.2019609","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2019608.2019609","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/2019608.2019609","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.4099999964237213,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2014468639.pdf","grobid_xml":"https://content.openalex.org/works/W2014468639.grobid-xml"},"referenced_works_count":38,"referenced_works":["https://openalex.org/W63944998","https://openalex.org/W184362337","https://openalex.org/W1539430313","https://openalex.org/W1946902536","https://openalex.org/W1991222965","https://openalex.org/W2015068790","https://openalex.org/W2019854215","https://openalex.org/W2032094184","https://openalex.org/W2073617099","https://openalex.org/W2086364491","https://openalex.org/W2092768095","https://openalex.org/W2097117297","https://openalex.org/W2117184662","https://openalex.org/W2127637835","https://openalex.org/W2127643746","https://openalex.org/W2132292283","https://openalex.org/W2139350452","https://openalex.org/W2143285027","https://openalex.org/W2144954274","https://openalex.org/W2145908511","https://openalex.org/W2148004594","https://openalex.org/W2149003795","https://openalex.org/W2153456949","https://openalex.org/W2154637658","https://openalex.org/W2158924248","https://openalex.org/W2163290010","https://openalex.org/W2163820265","https://openalex.org/W2170990025","https://openalex.org/W2171006257","https://openalex.org/W2292073965","https://openalex.org/W2294693415","https://openalex.org/W2337712060","https://openalex.org/W2487845934","https://openalex.org/W4240515487","https://openalex.org/W4247641071","https://openalex.org/W4252801914","https://openalex.org/W4298052798","https://openalex.org/W6602613798"],"related_works":["https://openalex.org/W4293430534","https://openalex.org/W2342813629","https://openalex.org/W3150934690","https://openalex.org/W2335743642","https://openalex.org/W4297812927","https://openalex.org/W2800412005","https://openalex.org/W2154976966","https://openalex.org/W1976244802","https://openalex.org/W2083934844","https://openalex.org/W1992487929"],"abstract_inverted_index":{"This":[0],"article":[1],"proposes":[2],"techniques":[3,69],"to":[4,76,87],"predict":[5],"the":[6],"performance":[7],"impact":[8,79],"of":[9,34,45,51,64,74,80,96],"pending":[10,35,52],"cache":[11],"hits,":[12],"hardware":[13],"prefetching,":[14,60],"and":[15,37,39,56],"miss":[16],"status":[17],"holding":[18],"register":[19],"resources":[20],"on":[21,32],"superscalar":[22],"microprocessors":[23],"using":[24,92],"hybrid":[25],"analytical":[26],"models.":[27],"The":[28,78],"proposed":[29],"models":[30],"focus":[31],"timeliness":[33],"hits":[36,53],"prefetches":[38],"account":[40],"for":[41],"a":[42,61,93],"limited":[43,62],"number":[44,63],"MSHRs.":[46],"They":[47],"improve":[48],"modeling":[49,58],"accuracy":[50],"by":[54,91],"3.9\u00d7":[55],"when":[57],"data":[59],"MSHRs,":[65],"or":[66],"both,":[67],"these":[68],"result":[70],"in":[71],"average":[72,95],"errors":[73],"9.5%":[75],"17.8%.":[77],"non-uniform":[81],"DRAM":[82],"memory":[83,97],"latency":[84],"is":[85],"shown":[86],"be":[88],"approximated":[89],"well":[90],"moving":[94],"access":[98],"latency.":[99]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":4}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}