{"id":"https://openalex.org/W2133602216","doi":"https://doi.org/10.1145/201310.201321","title":"The design of RPM","display_name":"The design of RPM","publication_year":1995,"publication_date":"1995-02-15","ids":{"openalex":"https://openalex.org/W2133602216","doi":"https://doi.org/10.1145/201310.201321","mag":"2133602216"},"language":"en","primary_location":{"id":"doi:10.1145/201310.201321","is_oa":true,"landing_page_url":"https://doi.org/10.1145/201310.201321","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/201310.201321","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/201310.201321","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001113375","display_name":"Koray \u00d6ner","orcid":null},"institutions":[{"id":"https://openalex.org/I4210116219","display_name":"Engineering Systems (United States)","ror":"https://ror.org/02qg60849","country_code":"US","type":"company","lineage":["https://openalex.org/I4210116219"]},{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Koray \u00d6ner","raw_affiliation_strings":["Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA","institution_ids":["https://openalex.org/I1174212","https://openalex.org/I4210116219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057539565","display_name":"Luiz Andr\u00e9 Barroso","orcid":"https://orcid.org/0000-0002-7854-9955"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]},{"id":"https://openalex.org/I4210116219","display_name":"Engineering Systems (United States)","ror":"https://ror.org/02qg60849","country_code":"US","type":"company","lineage":["https://openalex.org/I4210116219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Luiz A. Barroso","raw_affiliation_strings":["Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA","institution_ids":["https://openalex.org/I1174212","https://openalex.org/I4210116219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5104066149","display_name":"Sasan Iman","orcid":null},"institutions":[{"id":"https://openalex.org/I4210116219","display_name":"Engineering Systems (United States)","ror":"https://ror.org/02qg60849","country_code":"US","type":"company","lineage":["https://openalex.org/I4210116219"]},{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sasan Iman","raw_affiliation_strings":["Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA","institution_ids":["https://openalex.org/I1174212","https://openalex.org/I4210116219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101550276","display_name":"Jaeheon Jeong","orcid":"https://orcid.org/0000-0003-2540-600X"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]},{"id":"https://openalex.org/I4210116219","display_name":"Engineering Systems (United States)","ror":"https://ror.org/02qg60849","country_code":"US","type":"company","lineage":["https://openalex.org/I4210116219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jaeheon Jeong","raw_affiliation_strings":["Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA","institution_ids":["https://openalex.org/I1174212","https://openalex.org/I4210116219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011736193","display_name":"Krishnan Ramamurthy","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]},{"id":"https://openalex.org/I4210116219","display_name":"Engineering Systems (United States)","ror":"https://ror.org/02qg60849","country_code":"US","type":"company","lineage":["https://openalex.org/I4210116219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Krishnan Ramamurthy","raw_affiliation_strings":["Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA","institution_ids":["https://openalex.org/I1174212","https://openalex.org/I4210116219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102931397","display_name":"Michel Dubois","orcid":"https://orcid.org/0000-0002-8302-2330"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]},{"id":"https://openalex.org/I4210116219","display_name":"Engineering Systems (United States)","ror":"https://ror.org/02qg60849","country_code":"US","type":"company","lineage":["https://openalex.org/I4210116219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michel Dubois","raw_affiliation_strings":["Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA","institution_ids":["https://openalex.org/I1174212","https://openalex.org/I4210116219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5001113375"],"corresponding_institution_ids":["https://openalex.org/I1174212","https://openalex.org/I4210116219"],"apc_list":null,"apc_paid":null,"fwci":1.578,"has_fulltext":true,"cited_by_count":19,"citation_normalized_percentile":{"value":0.85267621,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"60","last_page":"66"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.9322253465652466},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7475923299789429},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7191016674041748},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6822457313537598},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6271835565567017},{"id":"https://openalex.org/keywords/hardware-emulation","display_name":"Hardware emulation","score":0.5164914131164551},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.5088124871253967},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.48668938875198364},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.4562046527862549},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.45299550890922546},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.4478130638599396},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.4197111427783966},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3773246705532074},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2832871973514557},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1634082794189453},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.11858946084976196}],"concepts":[{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.9322253465652466},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7475923299789429},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7191016674041748},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6822457313537598},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6271835565567017},{"id":"https://openalex.org/C94115699","wikidata":"https://www.wikidata.org/wiki/Q5656406","display_name":"Hardware emulation","level":3,"score":0.5164914131164551},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.5088124871253967},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.48668938875198364},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.4562046527862549},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.45299550890922546},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.4478130638599396},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.4197111427783966},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3773246705532074},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2832871973514557},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1634082794189453},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.11858946084976196},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/201310.201321","is_oa":true,"landing_page_url":"https://doi.org/10.1145/201310.201321","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/201310.201321","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/201310.201321","is_oa":true,"landing_page_url":"https://doi.org/10.1145/201310.201321","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/201310.201321","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.4099999964237213}],"awards":[{"id":"https://openalex.org/G4857055289","display_name":"The U.S.C. Multiprocessor Testbed: A Testbed for            Scalable Shared-Memory Systems","funder_award_id":"9223812","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2133602216.pdf","grobid_xml":"https://content.openalex.org/works/W2133602216.grobid-xml"},"referenced_works_count":10,"referenced_works":["https://openalex.org/W4097205","https://openalex.org/W25812913","https://openalex.org/W1966285605","https://openalex.org/W1975079715","https://openalex.org/W2044902313","https://openalex.org/W2106193445","https://openalex.org/W2122100378","https://openalex.org/W2127547524","https://openalex.org/W2133486861","https://openalex.org/W2156735174"],"related_works":["https://openalex.org/W2014165129","https://openalex.org/W2197466303","https://openalex.org/W2046817858","https://openalex.org/W1972395546","https://openalex.org/W2052520871","https://openalex.org/W2534453537","https://openalex.org/W2268234156","https://openalex.org/W2170906710","https://openalex.org/W1966262200","https://openalex.org/W2127780907"],"abstract_inverted_index":{"Recent":[0],"advances":[1],"in":[2,23,29],"Field-Programmable":[3],"Gate":[4],"Arrays":[5],"(FPGA)":[6],"and":[7],"programmable":[8],"interconnects":[9],"have":[10],"made":[11],"it":[12],"possible":[13],"to":[14,55],"build":[15],"efficient":[16],"hardware":[17,59],"emulation":[18,63],"engines.":[19],"In":[20],"addition,":[21],"improvements":[22],"Computer-Aided":[24],"Design":[25],"(CAD)":[26],"tools,":[27,31],"mainly":[28],"synthesis":[30],"greatly":[32],"simplify":[33],"the":[34,62],"design":[35],"of":[36,64],"large":[37],"circuits.":[38],"The":[39],"RPM":[40],"(Rapid":[41],"Prototype":[42],"Engine":[43],"for":[44,61],"Multiprocessors)":[45],"Project":[46],"leverages":[47],"these":[48],"two":[49],"technological":[50],"advances.":[51],"Its":[52],"goal":[53],"is":[54],"develop":[56],"a":[57],"common":[58],"platform":[60],"multiprocessor":[65],"systems":[66],"with":[67],"different":[68],"architectures.":[69]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2016-06-24T00:00:00"}