{"id":"https://openalex.org/W1980364632","doi":"https://doi.org/10.1145/2000064.2000094","title":"SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading","display_name":"SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading","publication_year":2011,"publication_date":"2011-06-04","ids":{"openalex":"https://openalex.org/W1980364632","doi":"https://doi.org/10.1145/2000064.2000094","mag":"1980364632"},"language":"en","primary_location":{"id":"doi:10.1145/2000064.2000094","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2000064.2000094","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 38th annual international symposium on Computer architecture","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110139710","display_name":"Wing-kei Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wing-kei S. Yu","raw_affiliation_strings":["Cornell University, Ithaca, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cornell University, Ithaca, NY, USA","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112210547","display_name":"Ruirui Huang","orcid":"https://orcid.org/0000-0003-4703-6038"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ruirui Huang","raw_affiliation_strings":["Cornell University, Ithaca, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cornell University, Ithaca, NY, USA","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050792872","display_name":"Sarah Q. Xu","orcid":null},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sarah Q. Xu","raw_affiliation_strings":["Cornell University, Ithaca, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cornell University, Ithaca, NY, USA","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059520814","display_name":"Sung-En Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sung-En Wang","raw_affiliation_strings":["Cornell University, Ithaca, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cornell University, Ithaca, NY, USA","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021345838","display_name":"Edwin C. Kan","orcid":"https://orcid.org/0000-0002-4733-4206"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Edwin Kan","raw_affiliation_strings":["Cornell University, Ithaca, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cornell University, Ithaca, NY, USA","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024329178","display_name":"G. Edward Suh","orcid":"https://orcid.org/0000-0001-6409-9888"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G. Edward Suh","raw_affiliation_strings":["Cornell University, Ithaca, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cornell University, Ithaca, NY, USA","institution_ids":["https://openalex.org/I205783295"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I205783295"],"apc_list":null,"apc_paid":null,"fwci":6.0805,"has_fulltext":false,"cited_by_count":79,"citation_normalized_percentile":{"value":0.97343039,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"247","last_page":"258"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.792654275894165},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6833063960075378},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6674222946166992},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.6461401581764221},{"id":"https://openalex.org/keywords/context-switch","display_name":"Context switch","score":0.5869277715682983},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5591332316398621},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.5547884702682495},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5132088661193848},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4418218731880188},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3812105655670166},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37167367339134216},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3267672061920166},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3170003890991211},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.2845305800437927},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.14246916770935059}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.792654275894165},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6833063960075378},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6674222946166992},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.6461401581764221},{"id":"https://openalex.org/C53833338","wikidata":"https://www.wikidata.org/wiki/Q1061424","display_name":"Context switch","level":2,"score":0.5869277715682983},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5591332316398621},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.5547884702682495},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5132088661193848},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4418218731880188},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3812105655670166},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37167367339134216},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3267672061920166},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3170003890991211},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.2845305800437927},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.14246916770935059}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2000064.2000094","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2000064.2000094","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 38th annual international symposium on Computer architecture","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W191948085","https://openalex.org/W1979527452","https://openalex.org/W2022740893","https://openalex.org/W2038061869","https://openalex.org/W2062419791","https://openalex.org/W2063388447","https://openalex.org/W2078994750","https://openalex.org/W2080592089","https://openalex.org/W2084416612","https://openalex.org/W2086157325","https://openalex.org/W2103206828","https://openalex.org/W2114429886","https://openalex.org/W2916411819","https://openalex.org/W3147067924"],"related_works":["https://openalex.org/W2000038758","https://openalex.org/W2122895920","https://openalex.org/W1974599144","https://openalex.org/W2546565930","https://openalex.org/W3185952280","https://openalex.org/W2736277924","https://openalex.org/W2105673382","https://openalex.org/W2087507048","https://openalex.org/W2246887984","https://openalex.org/W4254177552"],"abstract_inverted_index":{"Large":[0],"register":[1,39,140],"files":[2],"are":[3],"common":[4],"in":[5,61,67,97,139],"highly":[6],"multi-threaded":[7,38],"architectures":[8],"such":[9],"as":[10],"GPUs.":[11],"This":[12,64],"paper":[13],"presents":[14],"a":[15,28],"hybrid":[16,43,91],"memory":[17,92],"design":[18],"that":[19,55],"tightly":[20],"integrates":[21],"embedded":[22],"DRAM":[23,52,85,101],"into":[24],"SRAM":[25,46,76,150],"cells":[26,53],"with":[27,50,78,152],"main":[29],"application":[30],"to":[31,74,83,99,105,121],"reducing":[32],"area":[33,69,142],"and":[34,70,117,125,129,144],"power":[35],"consumption":[36],"of":[37,132],"files.":[40],"In":[41,103],"the":[42,75,79,90,122,126,148],"memory,":[44],"each":[45,62],"cell":[47],"is":[48],"augmented":[49],"multiple":[51,56],"so":[54],"bits":[57],"can":[58],"be":[59],"stored":[60],"cell.":[63],"configuration":[65],"results":[66],"significant":[68,137],"energy":[71,145],"savings":[72,138],"compared":[73],"array":[77],"same":[80],"capacity":[81],"due":[82],"compact":[84],"cells.":[86],"On":[87],"other":[88],"hand,":[89],"requires":[93],"explicit":[94],"data":[95],"movements":[96],"order":[98,104],"access":[100],"contexts.":[102],"minimize":[106],"context":[107,115],"switching":[108],"impact,":[109],"we":[110],"introduce":[111],"write-back":[112],"buffers,":[113],"background":[114],"switching,":[116],"context-aware":[118],"thread":[119],"scheduling,":[120],"processor":[123],"pipeline":[124],"scheduler.":[127],"Circuit":[128],"architecture":[130],"simulations":[131],"GPU":[133],"benchmarks":[134],"suites":[135],"show":[136],"file":[141],"(38%)":[143],"(68%)":[146],"over":[147],"traditional":[149],"implementation,":[151],"minimal":[153],"(1.4%)":[154],"performance":[155],"loss.":[156]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":8},{"year":2016,"cited_by_count":12},{"year":2015,"cited_by_count":15},{"year":2014,"cited_by_count":9},{"year":2013,"cited_by_count":15},{"year":2012,"cited_by_count":6}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}