{"id":"https://openalex.org/W2009371813","doi":"https://doi.org/10.1145/1988915.1988925","title":"The impact of diverse memory architectures on multicore consumer software","display_name":"The impact of diverse memory architectures on multicore consumer software","publication_year":2011,"publication_date":"2011-06-05","ids":{"openalex":"https://openalex.org/W2009371813","doi":"https://doi.org/10.1145/1988915.1988925","mag":"2009371813"},"language":"en","primary_location":{"id":"doi:10.1145/1988915.1988925","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1988915.1988925","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2011 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004495235","display_name":"George Russel","orcid":null},"institutions":[{"id":"https://openalex.org/I4210128426","display_name":"Codeplay (United Kingdom)","ror":"https://ror.org/03g46y557","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210128426"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"George Russel","raw_affiliation_strings":["Codeplay Software Ltd"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Codeplay Software Ltd","institution_ids":["https://openalex.org/I4210128426"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083847075","display_name":"Colin Riley","orcid":null},"institutions":[{"id":"https://openalex.org/I4210128426","display_name":"Codeplay (United Kingdom)","ror":"https://ror.org/03g46y557","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210128426"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Colin Riley","raw_affiliation_strings":["Codeplay Software Ltd"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Codeplay Software Ltd","institution_ids":["https://openalex.org/I4210128426"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025924502","display_name":"Neil Henning","orcid":null},"institutions":[{"id":"https://openalex.org/I4210128426","display_name":"Codeplay (United Kingdom)","ror":"https://ror.org/03g46y557","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210128426"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Neil Henning","raw_affiliation_strings":["Codeplay Software Ltd"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Codeplay Software Ltd","institution_ids":["https://openalex.org/I4210128426"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086448315","display_name":"Uwe Dolinsky","orcid":null},"institutions":[{"id":"https://openalex.org/I4210128426","display_name":"Codeplay (United Kingdom)","ror":"https://ror.org/03g46y557","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210128426"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Uwe Dolinsky","raw_affiliation_strings":["Codeplay Software Ltd"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Codeplay Software Ltd","institution_ids":["https://openalex.org/I4210128426"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048419992","display_name":"Andrew Richards","orcid":null},"institutions":[{"id":"https://openalex.org/I4210128426","display_name":"Codeplay (United Kingdom)","ror":"https://ror.org/03g46y557","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210128426"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Andrew Richards","raw_affiliation_strings":["Codeplay Software Ltd"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Codeplay Software Ltd","institution_ids":["https://openalex.org/I4210128426"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080781439","display_name":"Alastair F. Donaldson","orcid":"https://orcid.org/0000-0002-7448-7961"},"institutions":[{"id":"https://openalex.org/I40120149","display_name":"University of Oxford","ror":"https://ror.org/052gg0110","country_code":"GB","type":"education","lineage":["https://openalex.org/I40120149"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Alastair F. Donaldson","raw_affiliation_strings":["University of Oxford"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Oxford","institution_ids":["https://openalex.org/I40120149"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037460538","display_name":"A. S. van Amesfoort","orcid":null},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Alexander S. van Amesfoort","raw_affiliation_strings":["Delft University of Technology","Delft University of Technology,,,,,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Delft University of Technology","institution_ids":["https://openalex.org/I98358874"]},{"raw_affiliation_string":"Delft University of Technology,,,,,","institution_ids":["https://openalex.org/I98358874"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.08615611,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"37","last_page":"42"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.991599977016449,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8397982716560364},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6311972141265869},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6210108995437622},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5935729146003723},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5704009532928467},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5631168484687805},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5526167750358582},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.5343709588050842},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4522151052951813},{"id":"https://openalex.org/keywords/resource-oriented-architecture","display_name":"Resource-oriented architecture","score":0.4145370423793793},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.4071236848831177},{"id":"https://openalex.org/keywords/software-construction","display_name":"Software construction","score":0.38188207149505615},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.36104416847229004}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8397982716560364},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6311972141265869},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6210108995437622},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5935729146003723},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5704009532928467},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5631168484687805},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5526167750358582},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.5343709588050842},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4522151052951813},{"id":"https://openalex.org/C97382630","wikidata":"https://www.wikidata.org/wiki/Q13501132","display_name":"Resource-oriented architecture","level":5,"score":0.4145370423793793},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.4071236848831177},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.38188207149505615},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.36104416847229004}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1988915.1988925","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1988915.1988925","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2011 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5699999928474426}],"awards":[{"id":"https://openalex.org/G2705848627","display_name":null,"funder_award_id":"EP/G051100/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G8481226079","display_name":"Advanced Formal Verification Techniques for Heterogeneous Multi-core Programming","funder_award_id":"EP/G051100/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G8578266486","display_name":null,"funder_award_id":"248481","funder_id":"https://openalex.org/F4320334960","funder_display_name":"Seventh Framework Programme"},{"id":"https://openalex.org/G8834084293","display_name":null,"funder_award_id":"FP7/ICT 217068","funder_id":"https://openalex.org/F4320334960","funder_display_name":"Seventh Framework Programme"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"},{"id":"https://openalex.org/F4320334960","display_name":"Seventh Framework Programme","ror":"https://ror.org/00k4n6c32"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1605419350","https://openalex.org/W1963637299","https://openalex.org/W2080393180","https://openalex.org/W2085118703","https://openalex.org/W2092608522","https://openalex.org/W2117228145","https://openalex.org/W2126545867","https://openalex.org/W2145821613","https://openalex.org/W2148125582","https://openalex.org/W2159535674","https://openalex.org/W2160536499","https://openalex.org/W2197856798","https://openalex.org/W2399715892"],"related_works":["https://openalex.org/W2126179151","https://openalex.org/W2145298726","https://openalex.org/W2054763208","https://openalex.org/W2627074413","https://openalex.org/W39186842","https://openalex.org/W2032832792","https://openalex.org/W2357288334","https://openalex.org/W4378700939","https://openalex.org/W56096921","https://openalex.org/W1558214535"],"abstract_inverted_index":{"Memory":[0],"architectures":[1],"need":[2],"to":[3,11,84],"adapt":[4],"in":[5,14,54,67,87,90,116,135],"order":[6],"for":[7,16,28,72],"performance":[8,44],"and":[9,43,75,93,138],"scalability":[10],"be":[12],"achieved":[13],"software":[15,63,100],"multicore":[17],"systems.":[18],"In":[19],"this":[20,55],"paper,":[21],"we":[22,49,82],"discuss":[23,79],"the":[24,33,41,68,80,94,124,136],"impact":[25,95,113],"of":[26,35,45,70,118,140],"techniques":[27,129],"scalable":[29],"memory":[30,38,88],"architectures,":[31],"especially":[32],"use":[34,83],"multiple,":[36],"non-cache-coherent":[37],"spaces,":[39],"on":[40,99,114],"implementation":[42],"consumer":[46,91],"software.":[47,77],"Primarily,":[48],"report":[50],"extensive":[51],"real-world":[52],"experience":[53],"area":[56,69],"gained":[57],"by":[58],"Codeplay":[59],"Software":[60],"Ltd.,":[61],"a":[62,119,141],"tools":[64],"company":[65],"working":[66],"compilers":[71],"video":[73,145],"games":[74],"GPU":[76],"We":[78],"solutions":[81],"handle":[85],"variations":[86,97],"architecture":[89],"software,":[92,115],"such":[96],"have":[98,131],"development":[101,105,137],"effort":[102],"and,":[103],"consequently,":[104],"cost.":[106],"This":[107],"paper":[108],"introduces":[109],"preliminary":[110],"findings":[111],"regarding":[112],"advance":[117],"larger-scale":[120],"analysis":[121],"planned":[122],"over":[123],"next":[125],"few":[126],"years.":[127],"The":[128],"discussed":[130],"been":[132],"employed":[133],"successfully":[134],"optimisation":[139],"shipping":[142],"AAA":[143],"cross-platform":[144],"game.":[146]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}