{"id":"https://openalex.org/W2057195881","doi":"https://doi.org/10.1145/1980022.1980281","title":"Design and implementation of a universal DMA controller","display_name":"Design and implementation of a universal DMA controller","publication_year":2011,"publication_date":"2011-01-01","ids":{"openalex":"https://openalex.org/W2057195881","doi":"https://doi.org/10.1145/1980022.1980281","mag":"2057195881"},"language":"en","primary_location":{"id":"doi:10.1145/1980022.1980281","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1980022.1980281","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference &amp; Workshop on Emerging Trends in Technology - ICWET '11","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087570402","display_name":"Ameya Wadekar","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"A. Wadekar","raw_affiliation_strings":["GEC, Farmagudi, Goa"],"affiliations":[{"raw_affiliation_string":"GEC, Farmagudi, Goa","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089519700","display_name":"Sutar Swapnil","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Swapnil","raw_affiliation_strings":["MindTree, Bangaluru"],"affiliations":[{"raw_affiliation_string":"MindTree, Bangaluru","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074622629","display_name":"R. B. Lohani","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"R. B. Lohani","raw_affiliation_strings":["GEC, Farmagudi, Goa"],"affiliations":[{"raw_affiliation_string":"GEC, Farmagudi, Goa","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5087570402"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.11071872,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1189","last_page":"1189"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.992900013923645,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.992900013923645,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9883000254631042,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9731000065803528,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7548356056213379},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.7343623638153076},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.6984905004501343},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.6785429120063782},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.6772555708885193},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.6735820174217224},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.6407647132873535},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6304740905761719},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.6071029901504517},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.6040951609611511},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.5662010312080383},{"id":"https://openalex.org/keywords/direct-memory-access","display_name":"Direct memory access","score":0.5622382164001465},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5508995056152344},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.5441793203353882},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5284801721572876},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.521130383014679},{"id":"https://openalex.org/keywords/memory-address","display_name":"Memory address","score":0.49648648500442505},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.42993348836898804},{"id":"https://openalex.org/keywords/byte","display_name":"Byte","score":0.4191848933696747},{"id":"https://openalex.org/keywords/read-write-memory","display_name":"Read-write memory","score":0.4105762541294098},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.39172881841659546},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.37387537956237793},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.2871663570404053},{"id":"https://openalex.org/keywords/transfer","display_name":"Transfer (computing)","score":0.2771375775337219}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7548356056213379},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.7343623638153076},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.6984905004501343},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.6785429120063782},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.6772555708885193},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.6735820174217224},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.6407647132873535},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6304740905761719},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.6071029901504517},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.6040951609611511},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.5662010312080383},{"id":"https://openalex.org/C37724790","wikidata":"https://www.wikidata.org/wiki/Q210813","display_name":"Direct memory access","level":3,"score":0.5622382164001465},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5508995056152344},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.5441793203353882},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5284801721572876},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.521130383014679},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.49648648500442505},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.42993348836898804},{"id":"https://openalex.org/C43364308","wikidata":"https://www.wikidata.org/wiki/Q8799","display_name":"Byte","level":2,"score":0.4191848933696747},{"id":"https://openalex.org/C2776321774","wikidata":"https://www.wikidata.org/wiki/Q891131","display_name":"Read-write memory","level":3,"score":0.4105762541294098},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.39172881841659546},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.37387537956237793},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.2871663570404053},{"id":"https://openalex.org/C2776175482","wikidata":"https://www.wikidata.org/wiki/Q1195816","display_name":"Transfer (computing)","level":2,"score":0.2771375775337219},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1980022.1980281","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1980022.1980281","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference &amp; Workshop on Emerging Trends in Technology - ICWET '11","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7300000190734863,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2491097902","https://openalex.org/W4243333834","https://openalex.org/W2138847","https://openalex.org/W2501039532","https://openalex.org/W1554378476","https://openalex.org/W2381395788","https://openalex.org/W2057195881","https://openalex.org/W159027423","https://openalex.org/W2361382102","https://openalex.org/W2041174925"],"abstract_inverted_index":{"The":[0,51],"direct":[1,8],"memory":[2,12,49],"access":[3,9],"(DMA)":[4],"I/O":[5,43],"technique":[6],"provides":[7],"to":[10,90,95,100,106],"the":[11,14,24,33,37,78],"while":[13],"microprocessor":[15,34],"is":[16,59],"temporarily":[17,22],"disabled.":[18],"A":[19],"DMA":[20,57,68],"Controller":[21,58,69],"borrows":[23],"address":[25],"bus,":[26],"data":[27,38,80],"bus":[28,31],"and":[29,35,45,63,103,109],"control":[30],"from":[32],"transfers":[36],"bytes":[39],"directly":[40],"between":[41],"an":[42],"port":[44],"a":[46,55],"series":[47],"of":[48,54,60],"locations.":[50],"proposed":[52],"model":[53],"Universal":[56],"generic":[61],"type":[62],"supports":[64],"much":[65],"functionality.":[66],"This":[67],"can":[70],"be":[71],"plugged":[72],"into":[73],"any":[74],"SoC":[75],"system":[76],"for":[77],"required":[79],"transfer":[81],"operation.":[82],"Support":[83],"transactions":[84],"such":[85],"as":[86],"Port":[87],"1":[88],"IO/Memory":[89,94,99,102,105,108],"Port1":[91,93,101],"IO/Memory,":[92,97],"Port2":[96,98,104,107],"many":[110],"more.":[111]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
