{"id":"https://openalex.org/W1968442753","doi":"https://doi.org/10.1145/1980022.1980202","title":"FPGA prototype of 14 bit, 20msamples/S, 85 Mw successive approximation ADC suitable for RF applications","display_name":"FPGA prototype of 14 bit, 20msamples/S, 85 Mw successive approximation ADC suitable for RF applications","publication_year":2011,"publication_date":"2011-01-01","ids":{"openalex":"https://openalex.org/W1968442753","doi":"https://doi.org/10.1145/1980022.1980202","mag":"1968442753"},"language":"en","primary_location":{"id":"doi:10.1145/1980022.1980202","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1980022.1980202","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference & Workshop on Emerging Trends in Technology - ICWET '11","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062818574","display_name":"Rajendra D. Kanphade","orcid":"https://orcid.org/0000-0003-0474-136X"},"institutions":[{"id":"https://openalex.org/I4210153931","display_name":"D.Y. Patil University","ror":"https://ror.org/045qb5273","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210153931"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"R. D. Kanphade","raw_affiliation_strings":["Dhole Patil College of Engineering Pune, India"],"affiliations":[{"raw_affiliation_string":"Dhole Patil College of Engineering Pune, India","institution_ids":["https://openalex.org/I4210153931"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020841557","display_name":"Savita Patil","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]},{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. B. Patil","raw_affiliation_strings":["VLSI and ESD Centre, (Cadence and Xilinx Equipped), SGIARC, SSGMCE, Shegaon","VLSI and ESD Centre, (Cadence and Xilinx Equipped), SGIARC, SSGMCE, Shegaon#TAB#"],"affiliations":[{"raw_affiliation_string":"VLSI and ESD Centre, (Cadence and Xilinx Equipped), SGIARC, SSGMCE, Shegaon","institution_ids":["https://openalex.org/I66217453","https://openalex.org/I32923980"]},{"raw_affiliation_string":"VLSI and ESD Centre, (Cadence and Xilinx Equipped), SGIARC, SSGMCE, Shegaon#TAB#","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027957784","display_name":"Arun M. Patokar","orcid":"https://orcid.org/0000-0002-4846-7211"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. M. Patokar","raw_affiliation_strings":["VLSI and ESD Centre, (Cadence and Xilinx Equipped), SGIARC, SSGMCE, Shegaon","VLSI and ESD Centre, (Cadence and Xilinx Equipped), SGIARC, SSGMCE, Shegaon#TAB#"],"affiliations":[{"raw_affiliation_string":"VLSI and ESD Centre, (Cadence and Xilinx Equipped), SGIARC, SSGMCE, Shegaon","institution_ids":["https://openalex.org/I66217453","https://openalex.org/I32923980"]},{"raw_affiliation_string":"VLSI and ESD Centre, (Cadence and Xilinx Equipped), SGIARC, SSGMCE, Shegaon#TAB#","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045169115","display_name":"D. D. Nawgaje","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"D. D. Nawgaje","raw_affiliation_strings":["SSGM College of Engineering, Telecom, Shegaon MS, India"],"affiliations":[{"raw_affiliation_string":"SSGM College of Engineering, Telecom, Shegaon MS, India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5062818574"],"corresponding_institution_ids":["https://openalex.org/I4210153931"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05991214,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"832","last_page":"832"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9923999905586243,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8113775849342346},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7176780104637146},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6094086170196533},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5996309518814087},{"id":"https://openalex.org/keywords/matlab","display_name":"MATLAB","score":0.5307044386863708},{"id":"https://openalex.org/keywords/digital-to-analog-converter","display_name":"Digital-to-analog converter","score":0.44106751680374146},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.43513649702072144},{"id":"https://openalex.org/keywords/analog-to-digital-converter","display_name":"Analog-to-digital converter","score":0.41823461651802063},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4143243432044983},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3271491825580597},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14535295963287354},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13205817341804504}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8113775849342346},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7176780104637146},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6094086170196533},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5996309518814087},{"id":"https://openalex.org/C2780365114","wikidata":"https://www.wikidata.org/wiki/Q169478","display_name":"MATLAB","level":2,"score":0.5307044386863708},{"id":"https://openalex.org/C2779879419","wikidata":"https://www.wikidata.org/wiki/Q210863","display_name":"Digital-to-analog converter","level":3,"score":0.44106751680374146},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.43513649702072144},{"id":"https://openalex.org/C2777271169","wikidata":"https://www.wikidata.org/wiki/Q190169","display_name":"Analog-to-digital converter","level":3,"score":0.41823461651802063},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4143243432044983},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3271491825580597},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14535295963287354},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13205817341804504},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1980022.1980202","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1980022.1980202","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference & Workshop on Emerging Trends in Technology - ICWET '11","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.5899999737739563}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2087910249","https://openalex.org/W2110328984","https://openalex.org/W2154643998","https://openalex.org/W2164598631"],"related_works":["https://openalex.org/W2117342402","https://openalex.org/W2128735135","https://openalex.org/W1663661117","https://openalex.org/W2759986866","https://openalex.org/W2551040039","https://openalex.org/W2316679782","https://openalex.org/W2072062814","https://openalex.org/W3145876177","https://openalex.org/W582916503","https://openalex.org/W1981166077"],"abstract_inverted_index":{"ASIC":[0],"designing":[1],"for":[2,21,45],"analog":[3],"mixed-signal":[4],"ICs":[5],"is":[6,50,63,69,72,97],"bit":[7],"complicated":[8],"and":[9,65,82,100],"time":[10],"consuming.":[11],"Model-based":[12],"design":[13,19,24,62],"allows":[14],"us":[15],"to":[16],"complete":[17],"all":[18],"steps":[20],"validating":[22],"the":[23,26,59,61],"at":[25],"initial":[27],"stages.":[28],"In":[29],"this":[30],"work":[31],"a":[32,54],"14":[33],"bit,":[34],"20":[35],"MSamples/s,":[36],"85":[37],"mW":[38],"successive":[39],"approximation":[40],"analog-to-digital":[41],"converter":[42],"(ADC)":[43],"suitable":[44],"use":[46],"in":[47,74],"RF":[48],"applications":[49],"designed.":[51],"Beginning":[52],"with":[53],"high-level":[55],"behavioral":[56],"model":[57,91],"of":[58],"ADC,":[60],"elaborated":[64],"synthesizable":[66],"VeriLog":[67],"code":[68],"generated.":[70],"ADC":[71],"designed":[73],"Matlab's":[75],"Simulink":[76],"environment":[77],"using":[78,84],"system":[79],"generator,":[80],"simulated":[81],"synthesized":[83],"Xilinx's":[85,93],"ISE":[86],"9.1i.":[87],"Finally":[88],"we":[89],"prototyped":[90],"on":[92],"Spartan-II":[94],"FPGA":[95],"board":[96],"presented,":[98],"verified":[99],"results":[101],"are":[102],"presented.":[103]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}