{"id":"https://openalex.org/W2030754768","doi":"https://doi.org/10.1145/1973009.1973078","title":"Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems","display_name":"Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems","publication_year":2011,"publication_date":"2011-05-02","ids":{"openalex":"https://openalex.org/W2030754768","doi":"https://doi.org/10.1145/1973009.1973078","mag":"2030754768"},"language":"en","primary_location":{"id":"doi:10.1145/1973009.1973078","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1973009.1973078","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/168193","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026324911","display_name":"Pascal Meinerzhagen","orcid":"https://orcid.org/0000-0002-5444-5772"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Pascal Andreas Meinerzhagen","raw_affiliation_strings":["EPFL, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006449949","display_name":"Onur Andi\u00e7","orcid":null},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Onur Andi\u00e7","raw_affiliation_strings":["ETHZ, Zurich, Switzerland","ETHZ Zurich, Switzerland#TAB#"],"affiliations":[{"raw_affiliation_string":"ETHZ, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]},{"raw_affiliation_string":"ETHZ Zurich, Switzerland#TAB#","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059263528","display_name":"J\u00fcrg Treichler","orcid":null},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"J\u00fcrg Treichler","raw_affiliation_strings":["ETHZ, Zurich, Switzerland","ETHZ Zurich, Switzerland#TAB#"],"affiliations":[{"raw_affiliation_string":"ETHZ, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]},{"raw_affiliation_string":"ETHZ Zurich, Switzerland#TAB#","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059133771","display_name":"Andreas Burg","orcid":"https://orcid.org/0000-0002-7270-5558"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Andreas Peter Burg","raw_affiliation_strings":["EPFL, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5026324911"],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":null,"apc_paid":null,"fwci":1.3472,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.82459243,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"343","last_page":"346"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7265478372573853},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6993147730827332},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6946990489959717},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.5346336364746094},{"id":"https://openalex.org/keywords/data-retention","display_name":"Data retention","score":0.4808919429779053},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.47525712847709656},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.47127196192741394},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.45800966024398804},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.45581239461898804},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4439316391944885},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.42493578791618347},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.4226337671279907},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.34660956263542175},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.24568864703178406},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24171900749206543},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.19761121273040771},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1854758858680725},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.156612366437912},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.13036593794822693},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09203195571899414}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7265478372573853},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6993147730827332},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6946990489959717},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.5346336364746094},{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.4808919429779053},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.47525712847709656},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.47127196192741394},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.45800966024398804},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.45581239461898804},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4439316391944885},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.42493578791618347},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.4226337671279907},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34660956263542175},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.24568864703178406},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24171900749206543},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.19761121273040771},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1854758858680725},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.156612366437912},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.13036593794822693},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09203195571899414},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1973009.1973078","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1973009.1973078","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"},{"id":"pmh:oai:infoscience.epfl.ch:168193","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/168193","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:168193","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/168193","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1000572307","display_name":"Circuits and Systems for Next Generation Wireless Communication","funder_award_id":"119057","funder_id":"https://openalex.org/F4320320924","funder_display_name":"Schweizerischer Nationalfonds zur F\u00f6rderung der Wissenschaftlichen Forschung"},{"id":"https://openalex.org/G5921281487","display_name":null,"funder_award_id":"number","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G6187700389","display_name":null,"funder_award_id":"PP002-119057","funder_id":"https://openalex.org/F4320320924","funder_display_name":"Schweizerischer Nationalfonds zur F\u00f6rderung der Wissenschaftlichen Forschung"},{"id":"https://openalex.org/G848032724","display_name":null,"funder_award_id":"Science","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320320924","display_name":"Schweizerischer Nationalfonds zur F\u00f6rderung der Wissenschaftlichen Forschung","ror":"https://ror.org/00yjd3n13"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W603465109","https://openalex.org/W1491237044","https://openalex.org/W1598341975","https://openalex.org/W1871391557","https://openalex.org/W1940446526","https://openalex.org/W1977443758","https://openalex.org/W1982515552","https://openalex.org/W2106399682","https://openalex.org/W2114771440","https://openalex.org/W2115127472","https://openalex.org/W2116370472","https://openalex.org/W2140036368","https://openalex.org/W2154176871","https://openalex.org/W2163572715","https://openalex.org/W2167182882","https://openalex.org/W2562399749","https://openalex.org/W4205104605","https://openalex.org/W6680627514","https://openalex.org/W6684619581"],"related_works":["https://openalex.org/W2074922484","https://openalex.org/W2130607063","https://openalex.org/W2063061014","https://openalex.org/W2149227206","https://openalex.org/W2001316072","https://openalex.org/W2473808647","https://openalex.org/W3004383742","https://openalex.org/W2105633922","https://openalex.org/W2540867894","https://openalex.org/W1599111484"],"abstract_inverted_index":{"This":[0],"paper":[1],"considers":[2],"the":[3,7,24],"problem":[4],"of":[5,26,74],"increasing":[6],"storage":[8],"density":[9],"in":[10,46],"fault-tolerant":[11],"VLSI":[12],"systems":[13],"which":[14],"require":[15],"only":[16],"limited":[17],"data":[18],"retention":[19],"times.":[20],"To":[21],"this":[22],"end,":[23],"concept":[25],"storing":[27],"many":[28],"bits":[29],"per":[30],"memory":[31,44],"cell":[32],"is":[33,56],"applied":[34],"to":[35,62,68],"area-efficient":[36],"and":[37,53,58],"fully":[38],"logic-compatible":[39],"gain-cell-based":[40],"dynamic":[41],"memories.":[42],"A":[43],"macro":[45],"90-nm":[47],"CMOS":[48],"technology":[49],"including":[50],"multilevel":[51],"write":[52],"read":[54,64],"circuits":[55],"proposed":[57],"analyzed":[59],"with":[60],"respect":[61],"its":[63],"failure":[65],"probability":[66],"due":[67],"within-die":[69],"process":[70],"variations":[71],"by":[72],"means":[73],"Monte":[75],"Carlo":[76],"simulations.":[77]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-03-15T09:29:46.208133","created_date":"2025-10-10T00:00:00"}
